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netlist_carpentry.utils.gate_mixins

Classes:

ClkMixin

Bases: BaseModel

A mixin class for clocked gates. Clocked gates are gates that have a clock signal. This class provides a common interface for all clocked gates, including methods for evaluating the gate's output and setting its output signal.

Methods:

Attributes:

clk_polarity property writable 

clk_polarity: Signal

Which clock edge activates the flip-flop. Default is Signal.HIGH, i.e. rising edge.

clk_port property 

clk_port: Port[Instance]

The clock port of the gate.

model_post_init 

model_post_init(__context: object) -> None

Initializes the gate's ports and connections.

This method is called after the gate's attributes have been initialized, and it sets up the gate's ports and connections.

set_clk 

set_clk(new_signal: SignalOrLogicLevel) -> None

Sets the clock signal.

Parameters:

  • new_signal

    (Signal) –

    The new clock signal value.

EnMixin

Bases: BaseModel

Methods:

  • set_en –

    Sets the enable signal.

Attributes:

en_polarity property writable 

en_polarity: Signal

Which EN-signal level enables writing on the data storage. Default is Signal.HIGH.

en_port property 

en_port: Port[Instance]

The enable port of the gate.

en_signal property 

en_signal: Signal

The enable signal of the gate.

set_en 

set_en(new_signal: SignalOrLogicLevel) -> None

Sets the enable signal.

Parameters:

  • new_signal

    (Signal) –

    The new enable signal value.

RstMixin

Bases: BaseModel

Methods:

  • set_rst –

    Sets the reset signal.

Attributes:

  • rst_polarity (Signal) –

    Which reset level resets the flip-flop. Default is Signal.HIGH: the flipflop is in reset, if the reset signal is HIGH.

  • rst_val_int (int) –

    Reset value of the flip-flop as integer. Default is 0.

  • rst_port (Port[Instance]) –

    The reset port of the gate.

  • rst_val (SignalArray) –

    The value of the flipflop during and after reset. Default is Signal.LOW, i.e. the initial flipflop state is 0 by default.

  • in_reset (bool) –

    True if the gate is currently in reset, False otherwise.

rst_polarity property writable 

rst_polarity: Signal

Which reset level resets the flip-flop. Default is Signal.HIGH: the flipflop is in reset, if the reset signal is HIGH.

rst_val_int property writable 

rst_val_int: int

Reset value of the flip-flop as integer. Default is 0.

rst_port property 

rst_port: Port[Instance]

The reset port of the gate.

rst_val property 

rst_val: SignalArray

The value of the flipflop during and after reset. Default is Signal.LOW, i.e. the initial flipflop state is 0 by default.

in_reset property 

in_reset: bool

True if the gate is currently in reset, False otherwise.

set_rst 

set_rst(new_signal: SignalOrLogicLevel) -> None

Sets the reset signal.

Parameters:

  • new_signal

    (Signal) –

    The new reset signal value.

LoadMixin

Bases: BaseModel

Methods:

  • set_al –

    Sets the asynchronous load enable signal.

Attributes:

  • load_polarity (Signal) –

    Which load level loads the load value into flip-flop. Default is Signal.HIGH: the flipflop will load, if the load signal is HIGH.

  • al_port (Port[Instance]) –

    The asynchronous load enable port of the gate, i.e. the port that toggles whether to load data into the flip-flop.

  • ad_port (Port[Instance]) –

    The asynchronous data load port of the gate, i.e. the port that holds the data to load into the flip-flop.

  • load_val (SignalArray) –

    The value of the flipflop during and after reset, retrieved from the load data port.

  • load_val_int (Optional[int]) –

    The value of the flipflop during and after reset as an integer, retrieved from the load data port.

  • in_load (bool) –

    True if the gate is currently in "load-value" mode, False otherwise.

load_polarity property writable 

load_polarity: Signal

Which load level loads the load value into flip-flop. Default is Signal.HIGH: the flipflop will load, if the load signal is HIGH.

al_port property 

al_port: Port[Instance]

The asynchronous load enable port of the gate, i.e. the port that toggles whether to load data into the flip-flop.

ad_port property 

ad_port: Port[Instance]

The asynchronous data load port of the gate, i.e. the port that holds the data to load into the flip-flop.

load_val property 

load_val: SignalArray

The value of the flipflop during and after reset, retrieved from the load data port.

load_val_int property 

load_val_int: Optional[int]

The value of the flipflop during and after reset as an integer, retrieved from the load data port.

in_load property 

in_load: bool

True if the gate is currently in "load-value" mode, False otherwise.

set_al 

set_al(new_signal: SignalOrLogicLevel) -> None

Sets the asynchronous load enable signal.

Parameters:

  • new_signal

    (Signal) –

    The new asynchronous load enable signal value.

SRMixin

Bases: BaseModel

Methods:

Attributes:

  • clr_polarity (Signal) –

    Which clear level clears the flip-flop. Default is Signal.HIGH: the flipflop goes to 0, if the clear signal is HIGH.

  • clr_port (Port[Instance]) –

    The clear port of the gate.

  • set_polarity (Signal) –

    Which set level sets the flip-flop. Default is Signal.HIGH: the flipflop goes to 1, if the set signal is HIGH.

  • set_port (Port[Instance]) –

    The set port of the gate.

clr_polarity property writable 

clr_polarity: Signal

Which clear level clears the flip-flop. Default is Signal.HIGH: the flipflop goes to 0, if the clear signal is HIGH.

clr_port property 

clr_port: Port[Instance]

The clear port of the gate.

set_polarity property writable 

set_polarity: Signal

Which set level sets the flip-flop. Default is Signal.HIGH: the flipflop goes to 1, if the set signal is HIGH.

set_port property 

set_port: Port[Instance]

The set port of the gate.

set_clr 

set_clr(new_signal: SignalOrLogicLevel, idx: Union[int, List[int]]) -> None

Sets the clear signal.

Parameters:

  • new_signal

    (Signal) –

    The new clear signal value.

  • idx

    (Union[int, List[int]]) –

    The index (or indices) to apply the given signal to. Can either be an integer (single index to set) or an iterable of integers (e.g. a list of indices). For every integer of the iterable the signal value of the corresponding port index is set to the given new_signal. Defaults to 0.

set_set 

set_set(new_signal: SignalOrLogicLevel, idx: Union[int, List[int]]) -> None

Sets the set signal.

Parameters:

  • new_signal

    (Signal) –

    The new set signal value.

  • idx

    (Union[int, List[int]]) –

    The index (or indices) to apply the given signal to. Can either be an integer (single index to set) or an iterable of integers (e.g. a list of indices). For every integer of the iterable the signal value of the corresponding port index is set to the given new_signal. Defaults to 0.

ScanMixin

Bases: BaseModel

Methods:

  • set_se –

    Sets the scan enable signal.

Attributes:

se_signal property 

se_signal: Signal

The scan enable signal of the gate.

scan_ff_equivalent property 

scan_ff_equivalent: Type[ClkMixin]

Returns the Scan-FF type equivalent for normal FF and the FF type equivalent for Scan-FF.

set_se 

set_se(new_signal: SignalOrLogicLevel) -> None

Sets the scan enable signal.

Parameters:

  • new_signal

    (Signal) –

    The new scan enable signal value.