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netlist_carpentry.utils.gate_lib_extras

Classes:

  • BRAM –

    Represents a Yosys $mem_v2 memory cell as a primitive gate.

BRAM

Bases: ClkMixin, PrimitiveGate

Represents a Yosys $mem_v2 memory cell as a primitive gate.

Methods:

  • data_slice –

    Return a dict mapping bit-index → PortSegment for the data of port_idx.

  • addr_slice –

    Return a dict mapping bit-index → PortSegment for the address of port_idx.

  • en_array –

    Return enable-array info for a port (legacy API).

  • change_mutability –

    Change the mutability status of this instance and optionally its ports.

  • evaluate –

    Evaluates the gate's output signal based on its input signals.

  • all_connections –

    Returns a dictionary mapping port names to their corresponding connection paths.

  • connect –

    Add connections to the specified port of this instance.

  • disconnect –

    Remove an existing connection from a specified port of this instance.

  • get_connection –

    Retrieve the connection path associated with a specified port and bit index.

  • modify_connection –

    Modify an existing connection within a specified port of this instance.

  • connect_modify –

    Add a new connection or modify an existing one within the specified port of this instance.

  • tie_port –

    Set a constant signal value for the specified port and bit index.

  • has_tied_ports –

    Checks the ports of this instance whether any are tied to constant values.

  • has_tied_inputs –

    Checks the input ports of this instance whether any are tied to constant values.

  • has_tied_outputs –

    Checks the output ports of this instance whether any are tied to constant values.

  • update_signedness –

    Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

  • split –

    Performs a bit-wise split on this instance.

  • p2v –

    Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

  • ps2v –

    Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

  • set –

    Sets the signal on a port.

  • set_clk –

    Sets the clock signal.

Attributes:

width property 

width: PositiveInt

Data width of this BRAM (width of data input/output ports).

abits property 

abits: PositiveInt

Address width of this BRAM (width of address port).

clk_port property 

clk_port: PORT

BRAM has two clock ports — use rd_clk_port / wr_clk_port instead.

rd_clk_port property 

rd_clk_port: PORT

Read-clock port.

wr_clk_port property 

wr_clk_port: PORT

Write-clock port.

rd_addr_port property 

rd_addr_port: PORT

Read-address port.

wr_addr_port property 

wr_addr_port: PORT

Write-address port.

rd_data_port property 

rd_data_port: PORT

Read-data port.

wr_data_port property 

wr_data_port: PORT

Write-data port.

rd_en_port property 

rd_en_port: PORT

Read-enable port.

wr_en_port property 

wr_en_port: PORT

Write-enable port.

name instance-attribute 

name: str

The name of the element.

!!! Do not modify this variable after instantiating it. Use NetlistElement.set_name() instead. Modifying this variable might lead to inconsistencies later on.

metadata class-attribute instance-attribute 

metadata: MetadataMixin = MetadataMixin()

Metadata of a netlist element.

Can be user-defined, or e. g. by Yosys (such as src for the HDL source). Is also grouped by categories, i.e. all metadata from Yosys can be accessed via Module.metadata["yosys"], or via Module.metadata.yosys, which both return a dictionary of all metadata. Read the documentation of MetaDataMixin for more information.

path property 

path: InstancePath

Returns the InstancePath of the netlist element.

The InstancePath object is constructed using the element's type and its raw hierarchical path.

Returns:

  • InstancePath ( InstancePath ) –

    The hierarchical path of the netlist element.

type property 

type: EType

The type of the element, which is an instance.

hierarchy_level property 

hierarchy_level: int

The level of hierarchy of the element in the design.

The hierarchy level is the number of separators in the element's raw path. For example, a top-level instance has a hierarchy level of 0, while a direct submodule instance has a hierarchy level of 1.

Returns:

  • int ( int ) –

    The hierarchy level of the element.

has_parent property 

has_parent: bool

Whether this object has a parent.

circuit property 

circuit: 'Circuit'

The circuit object to which this netlist element belongs to.

  • For a module, returns the circuit to which the module belongs.
  • For any other netlist element, recursively returns the circuit of the parent, which ultimately leads to a module, to which the netlist element belongs.

Raises:

  • ParentNotFoundError –

    If a parent cannot be resolved somewhere in the hierarchical chain.

  • ObjectNotFoundError –

    If for a module no circuit is set.

has_circuit property 

has_circuit: bool

Whether this netlist element has a defined circuit it belongs to.

Tries to access self.circuit and returns whether the call was successful. Can be used instead of a try-except clause around the call to NetlistElement.circuit.

locked property 

locked: bool

True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

Can be changed via NetlistElement.change_mutability(bool).

Immutability is used to prevent accidental changes to the design.

is_placeholder_instance property 

is_placeholder_instance: bool

A placeholder represents an element that does not have a specific path.

True if this NetlistElement instance represents a placeholder, False otherwise.

can_carry_signal property 

can_carry_signal: bool

Whether this exact object is able to receive, pass or hold signal values.

True for ports (as they drive or receive values) and wires (as they pass the signals from driver to load ports) as well as their respective segments. False for instances and modules.

connections property 

connections: Dict[str, Dict[int, WireSegmentPath]]

A dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port. Elements with no connection (i.e. the path is None) are excluded. In case these are needed, use Instance.get_connections() instead.

Example

{ 'port1': {1: WireSegmentPath('path/to/element1'), 2: WireSegmentPath('path/to/element2')}, 'port2': {1: WireSegmentPath('path/to/element3')} }

connection_str_paths property 

connection_str_paths: Dict[str, Dict[int, str]]

Returns a dictionary mapping port names to their corresponding connection paths as strings.

The keys are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are the raw string paths.

Example

{ 'port1': {0: 'path.to.element1', 1: 'path.to.element2'}, 'port2': {0: 'path.to.element3'} }

ports property 

ports: CustomDict[str, Port[Instance]]

A dictionary mapping port names to their corresponding Port objects.

The keys of the dictionary are the names of the ports. The values are Port objects representing the ports.

Returns:

input_ports property 

input_ports: Tuple[Port[Instance], ...]

Returns a tuple of input ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as inputs.

Returns:

  • Tuple[Port[Instance], ...] –

    A tuple of Port objects representing the input ports.

output_ports property 

output_ports: Tuple[Port[Instance], ...]

Returns a tuple of output ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as outputs.

Returns:

  • Tuple[Port[Instance], ...] –

    A tuple of Port objects representing the output ports.

has_unconnected_port_segments property 

has_unconnected_port_segments: bool

Returns True if the instance has at least one unconnected port segment.

signals property 

signals: Dict[str, SignalArray]

A dictionary with all signals currently present on all ports of this instance.

is_blackbox property 

is_blackbox: bool

Flag indicating whether the instance represents neither a primitive element nor a module instance.

If True, this instance does not have a module definition, and is also not a basic component (i.e. a primitive gate instance) from the internal gate library, such as a gate or flip-flop.

splittable property 

splittable: bool

Whether n-bit wide instances of this type can be split into n 1-bit wide instances.

Supported for gate instances, where splitting does not change the overall behavior, e.g. splitting an 8-bit AND gate into 8 1-bit AND gates works fine, but an 8bit OR-REDUCE gate cannot be split, as this would change the behavior of the circuit.

y_width property 

y_width: PositiveInt

Width of the gate, based on a certain port's width, depending on the actual gate.

a_width property 

a_width: PositiveInt

Width of the gate's A port.

b_width property 

b_width: PositiveInt

Width of the gate's B port.

is_sequential property 

is_sequential: bool

Whether instances of this gate are considered sequential gates.

False for combinational gates, such as AND gates or arithmetic gates. True for flip-flops and latches.

output_port property 

output_port: Port[Instance]

The output port of the gate.

data_width property 

data_width: int

The data width of this instance.

Defaults to the data width of the output port. Can be overwritten in extended classes.

In contrast to self.width, which is used for the creation and initialization, this property is linked to the data width of the output port. This property is useful when the data width of the output port can be changed.

clk_polarity property writable 

clk_polarity: Signal

Which clock edge activates the flip-flop. Default is Signal.HIGH, i.e. rising edge.

data_slice 

data_slice(port_idx: int, rw: Literal['r', 'w']) -> Dict[int, PortSegment]

Return a dict mapping bit-index → PortSegment for the data of port_idx.

addr_slice 

addr_slice(port_idx: int, rw: Literal['r', 'w']) -> Dict[int, PortSegment]

Return a dict mapping bit-index → PortSegment for the address of port_idx.

en_array 

en_array(
    idx: int, rw: Literal["r", "w"]
) -> Dict[int, Union[Signal, PortSegment]]

Return enable-array info for a port (legacy API).

change_mutability 

change_mutability(is_now_locked: bool, recursive: bool = False) -> Self

Change the mutability status of this instance and optionally its ports.

This method allows setting whether this instance can be modified or not. If recursive is set to True, it also applies the same mutability status to all ports of this instance.

Parameters:

  • is_now_locked

    (bool) –

    The new mutability status for this instance.

  • recursive

    (bool, default: False ) –

    Whether to apply the change recursively to its ports. Defaults to False.

evaluate 

evaluate() -> None

Evaluates the gate's output signal based on its input signals.

This method is called when the gate's input signals change, and it updates the gate's output signal accordingly.

all_connections 

all_connections(
    include_unconnected: bool,
) -> Dict[str, Dict[int, WireSegmentPath]]

Returns a dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port.

Parameters:

  • include_unconnected

    (bool) –

    Whether to include unconnected ports in the result.

Returns:

connect 

connect(
    port_name: str,
    ws_path: Optional[WireSegmentPath],
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add connections to the specified port of this instance.

This method can establish multiple connections if a range of indices is provided.

Parameters:

  • port_name

    (str) –

    The name of the port where the connection(s) should be established.

  • ws_path

    (Optional[WireSegmentPath]) –

    The path of the wire segment that will be connected to this port. If None, the associated port (segment) remains unconnected.

  • direction

    (Direction, default: UNKNOWN ) –

    The direction of the port. Defaults to Direction.UNKNOWN.

  • index

    (NonNegativeInt, default: 0 ) –

    The starting bit index within the port for these connections. Defaults to 0.

  • width

    (PositiveInt, default: 1 ) –

    The number of consecutive bits in the port that should be connected. Defaults to 1.

Raises:

  • ObjectLockedError –

    If this instance is currently locked, and no connection can be made.

disconnect 

disconnect(port_name: str, index: Optional[int] = None) -> None

Remove an existing connection from a specified port of this instance.

This method disconnects the wire segment at the given index within the specified port_name.

Parameters:

  • port_name

    (str) –

    The name of the port where the connection should be removed.

  • index

    (Optional[int], default: None ) –

    The bit index within the port for this disconnection. Defaults to None, which completely disconnects the port.

Raises:

get_connection 

get_connection(
    port_name: str, index: Optional[NonNegativeInt] = None
) -> Union[WireSegmentPath, Dict[int, WireSegmentPath], None]

Retrieve the connection path associated with a specified port and bit index.

If index is provided, this method returns the wire segment path connected to that specific bit within the port. Otherwise, it returns all connections for the given port as a dictionary mapping indices to WireSegmentPaths.

Parameters:

  • port_name

    (str) –

    The name of the port for which to retrieve the connection(s).

  • index

    (Optional[NonNegativeInt], default: None ) –

    The bit index within the port. Defaults to None.

Returns:

modify_connection 

modify_connection(
    port_name: str, ws_path: WireSegmentPath, index: NonNegativeInt = 0
) -> None

Modify an existing connection within a specified port of this instance.

This method updates the wire segment path at the given index within the specified port_name. If the index does not exist yet, it is newly added, changing the width of the port.

Parameters:

  • port_name

    (str) –

    The name of the port where the connection should be modified.

  • ws_path

    (WireSegmentPath) –

    The new wire segment path for this connection.

  • index

    (NonNegativeInt, default: 0 ) –

    The bit index within the port. Defaults to 0.

connect_modify 

connect_modify(
    port_name: str,
    ws_path: WireSegmentPath,
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add a new connection or modify an existing one within the specified port of this instance.

If the connection already exists at the given index and port_name, it will be modified. Otherwise, a new connection is added.

Parameters:

  • port_name

    (str) –

    The name of the port where the connection should be established or updated.

  • ws_path

    (WireSegmentPath) –

    The path of the wire segment that will be connected to this port.

  • direction

    (Direction, default: UNKNOWN ) –

    The direction of the port. Defaults to Direction.UNKNOWN.

  • index

    (NonNegativeInt, default: 0 ) –

    The starting bit index within the port for these connections. Defaults to 0.

  • width

    (PositiveInt, default: 1 ) –

    The number of consecutive bits in the port that should be connected. Defaults to 1.

tie_port 

tie_port(name: str, index: NonNegativeInt, sig_value: LogicLevel) -> None

Set a constant signal value for the specified port and bit index.

If the specified port does not exist, an error message is logged and the function returns False. Otherwise, the method tries to set the constant signal value for that port and returns True if successful.

Does not work for instance output ports, as they are always driven by their parent instances.

Parameters:

  • name

    (str) –

    The name of the port.

  • index

    (NonNegativeInt) –

    The bit index within the port.

  • sig_value

    (LogicLevel) –

    The constant signal value to be set ('0', '1', or 'Z').

Raises:

  • ObjectNotFoundError –

    If no such port or port segment exists.

  • AlreadyConnectedError –

    (raised by: PortSegment.tie_signal) If this segment is belongs to a load port and is already connected to a wire, from which it receives its value.

  • InvalidDirectionError –

    (raised by: PortSegment.tie_signal) If this port segment belongs to an instance output port, which is driven by the instance inputs and the instance's internal logic.

  • InvalidSignalError –

    (raised by: PortSegment.tie_signal) If an invalid value is provided.

has_tied_ports 

has_tied_ports() -> bool

Checks the ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

  • bool ( bool ) –

    True if any ports of this instance are tied to constant values. False otherwise, i.e. all ports are connected to wires.

has_tied_inputs 

has_tied_inputs() -> bool

Checks the input ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

  • bool ( bool ) –

    True if any input ports of this instance are tied to constant values. False otherwise, i.e. all input ports are connected to wires.

has_tied_outputs 

has_tied_outputs() -> bool

Checks the output ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

  • bool ( bool ) –

    True if any output ports of this instance are tied to constant values. False otherwise, i.e. all output ports are connected to wires.

update_signedness 

update_signedness(port_name: str) -> None

Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

Parameters:

  • port_name

    (str) –

    The name of the port, of which the signedness value is retrieved.

split 

split() -> Dict[NonNegativeInt, Self]

Performs a bit-wise split on this instance.

If this instance supports splitting and has a data width of n bit, this method splits this instance into n 1-bit instances. This works for instances, where each output bit depends only on the corresponding input bit(s), e.g. an AND gate or a D-Flipflop.

Returns:

  • Dict[NonNegativeInt, Self] –

    Dict[int, Instance]: An n-bit large dictionary, where each key conforms to a bit of the original instance, and each value is an 1-bit instance representing the corresponding "slice" of the original instance.

Raises:

  • SplittingUnsupportedError –

    If this instance does not support splitting. Happens for any gate or instance whose behavior depends on the whole bus, and splitting would make it lose its meaning.

p2v 

p2v(
    port: ANY_PORT,
    exclude_indices: Optional[List[int]] = None,
    include_indices: Optional[List[int]] = None,
) -> str

Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a Port object and converts them to their corresponding Verilog signal structure (p2v -> Port to Verilog signal syntax). For each segment of the port, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port is set to a constant, the corresponding constant wire segment placeholder is used instead. Port segments can be excluded from the conversion by providing a list of indices to the exclude_indices parameter, indicating which segments should be excluded from the conversion (e.g. segments that are known to be unconnected). Vice versa, only a certain subset of the port's segments may be converted to Verilog syntax, if include_indices is a given list of port indices. All indices not present in the list will be excluded from the conversion.

Parameters:

  • port

    (Port) –

    The Port object to convert.

  • exclude_indices

    (List[int], default: None ) –

    A list of indices to exclude from the conversion. Defaults to None.

  • include_indices

    (List[int], default: None ) –

    A list of indices (i.e. port slices) to include only for the conversion. Defaults to None.

Returns:

  • str ( str ) –

    The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

  • ObjectNotFoundError –

    If the wire connected to a certain port segment could not be found.

  • UnsupportedOperationError –

    If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

ps2v 

ps2v(ps_dict: Dict[int, PortSegment]) -> str

Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a PortSegment dictionary and converts them to their corresponding Verilog signal structure (ps2v -> PortSegment to Verilog signal syntax). For each segment, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port segment is set to a constant, the corresponding constant wire segment placeholder is used instead.

Parameters:

  • ps_dict

    (Dict[int, PortSegment]) –

    The PortSegment dictionary to convert. Each key (int) conforms to the index of the associated PortSegment object.

Returns:

  • str ( str ) –

    The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

set 

set(
    port_name: str,
    new_signal: SignalOrLogicLevel,
    idx: Union[int, List[int]] = 0,
) -> None

Sets the signal on a port.

Parameters:

  • port_name

    (str) –

    The name of the port to set the signal on.

  • new_signal

    (Signal) –

    The new signal value.

  • idx

    (Union[int, List[int]], default: 0 ) –

    The index (or indices) to apply the given signal to. Can either be an integer (single index to set) or an iterable of integers (e.g. a list of indices). For every integer of the iterable the signal value of the corresponding port index is set to the given new_signal. Defaults to 0.

Example

from netlist_carpentry.utils.gate_factory import and_gate module = Module(name='m') a = module.create_port('a', 'input', width=6) instance = and_gate(module, 'inst', A=a)

This sets the value of bit 0 of port A to HIGH

instance.set('A', 1, 0) instance.ports['A'].signal_str 'xxxxx1'

This sets the value of bits 1, 3 and 5 of port A to LOW, leaving the other bits as they already are.

instance.set('A', 0, [1, 3, 5]) instance.ports['A'].signal_str '0x0x01'

set_clk 

set_clk(new_signal: SignalOrLogicLevel) -> None

Sets the clock signal.

Parameters:

  • new_signal

    (Signal) –

    The new clock signal value.