netlist_carpentry.utils.gate_lib_base_classes

This module provides a set of classes for modeling digital circuits at the gate level. It currently includes base classes for primitive gates, unary gates, binary gates, and clocked gates, as well as methods for evaluating the output signals of these gates. They provide a common interface for working with different types of gates, including methods for setting input signals, evaluating output signals, and updating gate states. See the gate_lib.py module for further information.

Classes:

• PrimitiveGate –

  A base class for all primitive gates.

• UnaryGate –

  A base class for unary gates.

• ReduceGate –

  A base class for reduce gates.

• BinaryGate –

  A base class for binary gates.

• ArithmeticGate –

  A base class for arithmetic gates.

• BinaryNto1Gate –
• NtoOneGate –

  Base class for gates with N data inputs and 1 output (e.g., multiplexers).

• OneToNGate –

  Base class for gates with 1 input and N data outputs (e.g., demultiplexers).

• StorageGate –

PrimitiveGate

Bases: Instance, BaseModel

A base class for all primitive gates.

Primitive gates are the basic building blocks of digital circuits, and they can be combined to create more complex circuits. This class provides a common interface for all primitive gates, including methods for evaluating the gate's output and setting its output signal.

Methods:

• p2v –

  Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

• ps2v –

  Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

• set –

  Sets the signal on a port.

• evaluate –

  Evaluates the gate's output signal based on its input signals.

• change_mutability –

  Change the mutability status of this instance and optionally its ports.

• all_connections –

  Returns a dictionary mapping port names to their corresponding connection paths.

• connect –

  Add connections to the specified port of this instance.

• disconnect –

  Remove an existing connection from a specified port of this instance.

• get_connection –

  Retrieve the connection path associated with a specified port and bit index.

• modify_connection –

  Modify an existing connection within a specified port of this instance.

• connect_modify –

  Add a new connection or modify an existing one within the specified port of this instance.

• tie_port –

  Set a constant signal value for the specified port and bit index.

• has_tied_ports –

  Checks the ports of this instance whether any are tied to constant values.

• has_tied_inputs –

  Checks the input ports of this instance whether any are tied to constant values.

• has_tied_outputs –

  Checks the output ports of this instance whether any are tied to constant values.

• update_signedness –

  Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

• split –

  Performs a bit-wise split on this instance.

Attributes:

• instance_type (str) –

  Identifier for instances of this gate type.

• parameters (GateParams) –

  Parameters of this gate, e.g. data width, signedness or polarity.

• y_width (PositiveInt) –

  Width of the gate, based on a certain port's width, depending on the actual gate.

• a_width (PositiveInt) –

  Width of the gate's A port.

• b_width (PositiveInt) –

  Width of the gate's B port.

• is_combinational (bool) –

  Whether instances of this gate are considered combinational gates.

• is_sequential (bool) –

  Whether instances of this gate are considered sequential gates.

• output_port (Port[Instance]) –

  The output port of the gate.

• data_width (int) –

  The data width of this instance.

• verilog_net_map (Dict[str, str]) –

  The parts of the Verilog representation of this gate instance as a dict.

• name (str) –

  The name of the element.

• metadata (MetadataMixin) –

  Metadata of a netlist element.

• path (InstancePath) –

  Returns the InstancePath of the netlist element.

• type (EType) –

  The type of the element, which is an instance.

• hierarchy_level (int) –

  The level of hierarchy of the element in the design.

• has_parent (bool) –

  Whether this object has a parent.

• circuit ('Circuit') –

  The circuit object to which this netlist element belongs to.

• has_circuit (bool) –

  Whether this netlist element has a defined circuit it belongs to.

• locked (bool) –

  True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

• is_placeholder_instance (bool) –

  A placeholder represents an element that does not have a specific path.

• can_carry_signal (bool) –

  Whether this exact object is able to receive, pass or hold signal values.

• connections (Dict[str, Dict[int, WireSegmentPath]]) –

  A dictionary mapping port names to their corresponding connection paths.

• connection_str_paths (Dict[str, Dict[int, str]]) –

  Returns a dictionary mapping port names to their corresponding connection paths as strings.

• ports (CustomDict[str, Port[Instance]]) –

  A dictionary mapping port names to their corresponding Port objects.

• input_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of input ports associated with this instance.

• output_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of output ports associated with this instance.

• has_unconnected_port_segments (bool) –

  Returns True if the instance has at least one unconnected port segment.

• signals (Dict[str, SignalArray]) –

  A dictionary with all signals currently present on all ports of this instance.

• is_blackbox (bool) –

  Flag indicating whether the instance represents neither a primitive element nor a module instance.

• splittable (bool) –

  Whether n-bit wide instances of this type can be split into n 1-bit wide instances.

• verilog (str) –

  Generates the Verilog code for this instance.

instance_type class-attribute instance-attribute

instance_type: str = CFG.id_internal

Identifier for instances of this gate type.

parameters class-attribute instance-attribute

parameters: GateParams = GateParams()

Parameters of this gate, e.g. data width, signedness or polarity.

y_width property

y_width: PositiveInt

Width of the gate, based on a certain port's width, depending on the actual gate.

a_width property

a_width: PositiveInt

Width of the gate's A port.

b_width property

b_width: PositiveInt

Width of the gate's B port.

is_combinational property

is_combinational: bool

Whether instances of this gate are considered combinational gates.

True for combinational gates, such as AND gates or arithmetic gates. False for flip-flops and latches.

is_sequential property

is_sequential: bool

Whether instances of this gate are considered sequential gates.

False for combinational gates, such as AND gates or arithmetic gates. True for flip-flops and latches.

output_port property

output_port: Port[Instance]

The output port of the gate.

data_width property

data_width: int

The data width of this instance.

Defaults to the data width of the output port. Can be overwritten in extended classes.

In contrast to self.width, which is used for the creation and initialization, this property is linked to the data width of the output port. This property is useful when the data width of the output port can be changed.

verilog_net_map property

verilog_net_map: Dict[str, str]

The parts of the Verilog representation of this gate instance as a dict.

If this gate is an AND gate, and the Verilog representation of this gate would be assign wire_out = wire1 & wire2;, then this dict is:

{
    "Y": "wire_out",
    "A": "wire1",
    "B": "wire2",
}

name instance-attribute

name: str

The name of the element.

!!! Do not modify this variable after instantiating it. Use NetlistElement.set_name() instead. Modifying this variable might lead to inconsistencies later on.

metadata class-attribute instance-attribute

metadata: MetadataMixin = MetadataMixin()

Metadata of a netlist element.

Can be user-defined, or e. g. by Yosys (such as src for the HDL source). Is also grouped by categories, i.e. all metadata from Yosys can be accessed via Module.metadata["yosys"], or via Module.metadata.yosys, which both return a dictionary of all metadata. Read the documentation of MetaDataMixin for more information.

path property

path: InstancePath

Returns the InstancePath of the netlist element.

The InstancePath object is constructed using the element's type and its raw hierarchical path.

Returns:

• InstancePath ( InstancePath ) –

  The hierarchical path of the netlist element.

type property

type: EType

The type of the element, which is an instance.

hierarchy_level property

hierarchy_level: int

The level of hierarchy of the element in the design.

The hierarchy level is the number of separators in the element's raw path. For example, a top-level instance has a hierarchy level of 0, while a direct submodule instance has a hierarchy level of 1.

Returns:

• int ( int ) –

  The hierarchy level of the element.

has_parent property

has_parent: bool

Whether this object has a parent.

circuit property

circuit: 'Circuit'

The circuit object to which this netlist element belongs to.

• For a module, returns the circuit to which the module belongs.
• For any other netlist element, recursively returns the circuit of the parent, which ultimately leads to a module, to which the netlist element belongs.

Raises:

• ParentNotFoundError –

  If a parent cannot be resolved somewhere in the hierarchical chain.

• ObjectNotFoundError –

  If for a module no circuit is set.

has_circuit property

has_circuit: bool

Whether this netlist element has a defined circuit it belongs to.

Tries to access self.circuit and returns whether the call was successful. Can be used instead of a try-except clause around the call to NetlistElement.circuit.

locked property

locked: bool

True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

Can be changed via NetlistElement.change_mutability(bool).

Immutability is used to prevent accidental changes to the design.

is_placeholder_instance property

is_placeholder_instance: bool

A placeholder represents an element that does not have a specific path.

True if this NetlistElement instance represents a placeholder, False otherwise.

can_carry_signal property

can_carry_signal: bool

Whether this exact object is able to receive, pass or hold signal values.

True for ports (as they drive or receive values) and wires (as they pass the signals from driver to load ports) as well as their respective segments. False for instances and modules.

connections property

connections: Dict[str, Dict[int, WireSegmentPath]]

A dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port. Elements with no connection (i.e. the path is None) are excluded. In case these are needed, use Instance.get_connections() instead.

Example

{ 'port1': {1: WireSegmentPath('path/to/element1'), 2: WireSegmentPath('path/to/element2')}, 'port2': {1: WireSegmentPath('path/to/element3')} }

connection_str_paths property

connection_str_paths: Dict[str, Dict[int, str]]

Returns a dictionary mapping port names to their corresponding connection paths as strings.

The keys are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are the raw string paths.

Example

{ 'port1': {0: 'path.to.element1', 1: 'path.to.element2'}, 'port2': {0: 'path.to.element3'} }

ports property

ports: CustomDict[str, Port[Instance]]

A dictionary mapping port names to their corresponding Port objects.

The keys of the dictionary are the names of the ports. The values are Port objects representing the ports.

Returns:

• CustomDict[str, Port[Instance]] –

  A dictionary mapping port names to their corresponding Port objects.

input_ports property

input_ports: Tuple[Port[Instance], ...]

Returns a tuple of input ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as inputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the input ports.

output_ports property

output_ports: Tuple[Port[Instance], ...]

Returns a tuple of output ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as outputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the output ports.

has_unconnected_port_segments property

has_unconnected_port_segments: bool

Returns True if the instance has at least one unconnected port segment.

signals property

signals: Dict[str, SignalArray]

A dictionary with all signals currently present on all ports of this instance.

is_blackbox property

is_blackbox: bool

Flag indicating whether the instance represents neither a primitive element nor a module instance.

If True, this instance does not have a module definition, and is also not a basic component (i.e. a primitive gate instance) from the internal gate library, such as a gate or flip-flop.

splittable property

splittable: bool

Whether n-bit wide instances of this type can be split into n 1-bit wide instances.

Supported for gate instances, where splitting does not change the overall behavior, e.g. splitting an 8-bit AND gate into 8 1-bit AND gates works fine, but an 8bit OR-REDUCE gate cannot be split, as this would change the behavior of the circuit.

verilog property

verilog: str

Generates the Verilog code for this instance.

This property uses the verilog_template to generate the actual Verilog code by replacing the placeholders with the instance type, name, and port connections. It returns a string that can be used directly in a Verilog file.

Returns:

• str ( str ) –

  The generated Verilog code.

p2v

p2v(
    port: ANY_PORT,
    exclude_indices: Optional[List[int]] = None,
    include_indices: Optional[List[int]] = None,
) -> str

Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a Port object and converts them to their corresponding Verilog signal structure (p2v -> Port to Verilog signal syntax). For each segment of the port, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port is set to a constant, the corresponding constant wire segment placeholder is used instead. Port segments can be excluded from the conversion by providing a list of indices to the exclude_indices parameter, indicating which segments should be excluded from the conversion (e.g. segments that are known to be unconnected). Vice versa, only a certain subset of the port's segments may be converted to Verilog syntax, if include_indices is a given list of port indices. All indices not present in the list will be excluded from the conversion.

Parameters:

• port

  (Port) –

  The Port object to convert.

• exclude_indices

  (List[int], default: None ) –

  A list of indices to exclude from the conversion. Defaults to None.

• include_indices

  (List[int], default: None ) –

  A list of indices (i.e. port slices) to include only for the conversion. Defaults to None.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

ps2v

ps2v(ps_dict: Dict[int, PortSegment]) -> str

Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a PortSegment dictionary and converts them to their corresponding Verilog signal structure (ps2v -> PortSegment to Verilog signal syntax). For each segment, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port segment is set to a constant, the corresponding constant wire segment placeholder is used instead.

Parameters:

• ps_dict

  (Dict[int, PortSegment]) –

  The PortSegment dictionary to convert. Each key (int) conforms to the index of the associated PortSegment object.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

• UnsupportedOperationError –

  If two segments belong to different modules.

set

set(
    port_name: str,
    new_signal: SignalOrLogicLevel,
    idx: Union[int, List[int]] = 0,
) -> None

Sets the signal on a port.

Parameters:

• port_name

  (str) –

  The name of the port to set the signal on.

• new_signal

  (Signal) –

  The new signal value.

• idx

  (Union[int, List[int]], default: 0 ) –

  The index (or indices) to apply the given signal to. Can either be an integer (single index to set) or an iterable of integers (e.g. a list of indices). For every integer of the iterable the signal value of the corresponding port index is set to the given new_signal. Defaults to 0.

Example

from netlist_carpentry.utils.gate_factory import and_gate module = Module(name='m') a = module.create_port('a', 'input', width=6) instance = and_gate(module, 'inst', A=a)

This sets the value of bit 0 of port A to HIGH

instance.set('A', 1, 0) instance.ports['A'].signal_str 'xxxxx1'

This sets the value of bits 1, 3 and 5 of port A to LOW, leaving the other bits as they already are.

instance.set('A', 0, [1, 3, 5]) instance.ports['A'].signal_str '0x0x01'

evaluate

evaluate() -> None

Evaluates the gate's output signal based on its input signals.

This method is called when the gate's input signals change, and it updates the gate's output signal accordingly.

change_mutability

change_mutability(is_now_locked: bool, recursive: bool = False) -> Self

Change the mutability status of this instance and optionally its ports.

This method allows setting whether this instance can be modified or not. If recursive is set to True, it also applies the same mutability status to all ports of this instance.

Parameters:

• is_now_locked

  (bool) –

  The new mutability status for this instance.

• recursive

  (bool, default: False ) –

  Whether to apply the change recursively to its ports. Defaults to False.

all_connections

all_connections(
    include_unconnected: bool,
) -> Dict[str, Dict[int, WireSegmentPath]]

Returns a dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port.

Parameters:

• include_unconnected

  (bool) –

  Whether to include unconnected ports in the result.

Returns:

• Dict[str, Dict[int, WireSegmentPath]] –

  A dictionary mapping port names to their corresponding connection paths.

connect

connect(
    port_name: str,
    ws_path: Optional[WireSegmentPath],
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add connections to the specified port of this instance.

This method can establish multiple connections if a range of indices is provided.

Parameters:

• port_name

  (str) –

  The name of the port where the connection(s) should be established.

• ws_path

  (Optional[WireSegmentPath]) –

  The path of the wire segment that will be connected to this port. If None, the associated port (segment) remains unconnected.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

Raises:

• ObjectLockedError –

  If this instance is currently locked, and no connection can be made.

disconnect

disconnect(port_name: str, index: Optional[int] = None) -> None

Remove an existing connection from a specified port of this instance.

This method disconnects the wire segment at the given index within the specified port_name.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be removed.

• index

  (Optional[int], default: None ) –

  The bit index within the port for this disconnection. Defaults to None, which completely disconnects the port.

Raises:

• ObjectLockedError –

  If this instance is locked.

• ObjectNotFoundError –

  If no port exists with the given name.

get_connection

get_connection(
    port_name: str, index: Optional[NonNegativeInt] = None
) -> Union[WireSegmentPath, Dict[int, WireSegmentPath], None]

Retrieve the connection path associated with a specified port and bit index.

If index is provided, this method returns the wire segment path connected to that specific bit within the port. Otherwise, it returns all connections for the given port as a dictionary mapping indices to WireSegmentPaths.

Parameters:

• port_name

  (str) –

  The name of the port for which to retrieve the connection(s).

• index

  (Optional[NonNegativeInt], default: None ) –

  The bit index within the port. Defaults to None.

Returns:

• Union[WireSegmentPath, Dict[int, WireSegmentPath], None] –

  Union[WireSegmentPath, Dict[int, WireSegmentPath]]: Either a single WireSegmentPath or a dictionary mapping indices to WireSegmentPaths.

modify_connection

modify_connection(
    port_name: str, ws_path: WireSegmentPath, index: NonNegativeInt = 0
) -> None

Modify an existing connection within a specified port of this instance.

This method updates the wire segment path at the given index within the specified port_name. If the index does not exist yet, it is newly added, changing the width of the port.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be modified.

• ws_path

  (WireSegmentPath) –

  The new wire segment path for this connection.

• index

  (NonNegativeInt, default: 0 ) –

  The bit index within the port. Defaults to 0.

connect_modify

connect_modify(
    port_name: str,
    ws_path: WireSegmentPath,
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add a new connection or modify an existing one within the specified port of this instance.

If the connection already exists at the given index and port_name, it will be modified. Otherwise, a new connection is added.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be established or updated.

• ws_path

  (WireSegmentPath) –

  The path of the wire segment that will be connected to this port.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

tie_port

tie_port(name: str, index: NonNegativeInt, sig_value: LogicLevel) -> None

Set a constant signal value for the specified port and bit index.

If the specified port does not exist, an error message is logged and the function returns False. Otherwise, the method tries to set the constant signal value for that port and returns True if successful.

Does not work for instance output ports, as they are always driven by their parent instances.

Parameters:

• name

  (str) –

  The name of the port.

• index

  (NonNegativeInt) –

  The bit index within the port.

• sig_value

  (LogicLevel) –

  The constant signal value to be set ('0', '1', or 'Z').

Raises:

• ObjectNotFoundError –

  If no such port or port segment exists.

• AlreadyConnectedError –

  (raised by: PortSegment.tie_signal) If this segment is belongs to a load port and is already connected to a wire, from which it receives its value.

• InvalidDirectionError –

  (raised by: PortSegment.tie_signal) If this port segment belongs to an instance output port, which is driven by the instance inputs and the instance's internal logic.

• InvalidSignalError –

  (raised by: PortSegment.tie_signal) If an invalid value is provided.

has_tied_ports

has_tied_ports() -> bool

Checks the ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any ports of this instance are tied to constant values. False otherwise, i.e. all ports are connected to wires.

has_tied_inputs

has_tied_inputs() -> bool

Checks the input ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any input ports of this instance are tied to constant values. False otherwise, i.e. all input ports are connected to wires.

has_tied_outputs

has_tied_outputs() -> bool

Checks the output ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any output ports of this instance are tied to constant values. False otherwise, i.e. all output ports are connected to wires.

update_signedness

update_signedness(port_name: str) -> None

Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

Parameters:

• port_name

  (str) –

  The name of the port, of which the signedness value is retrieved.

split

split() -> Dict[NonNegativeInt, Self]

Performs a bit-wise split on this instance.

If this instance supports splitting and has a data width of n bit, this method splits this instance into n 1-bit instances. This works for instances, where each output bit depends only on the corresponding input bit(s), e.g. an AND gate or a D-Flipflop.

Returns:

• Dict[NonNegativeInt, Self] –

  Dict[int, Instance]: An n-bit large dictionary, where each key conforms to a bit of the original instance, and each value is an 1-bit instance representing the corresponding "slice" of the original instance.

Raises:

• SplittingUnsupportedError –

  If this instance does not support splitting. Happens for any gate or instance whose behavior depends on the whole bus, and splitting would make it lose its meaning.

UnaryGate

Bases: PrimitiveGate, BaseModel

A base class for unary gates.

Unary gates are gates that have a single input signal, and they produce a single output signal. This class provides a common interface for all unary gates, including methods for evaluating the gate's output and setting its output signal.

Methods:

• model_post_init –

  Initializes the gate's ports and connections.

• get_result –

  Returns the result of this gate's operation for given Signal s.

• get_result_vector –

  Returns the result of this gate's operation for a full signal vector.

• signal_in –

  The input signal of the gate.

• signal_out –

  The output signal of the gate.

• change_mutability –

  Change the mutability status of this instance and optionally its ports.

• evaluate –

  Evaluates the gate's output signal based on its input signals.

• all_connections –

  Returns a dictionary mapping port names to their corresponding connection paths.

• connect –

  Add connections to the specified port of this instance.

• disconnect –

  Remove an existing connection from a specified port of this instance.

• get_connection –

  Retrieve the connection path associated with a specified port and bit index.

• modify_connection –

  Modify an existing connection within a specified port of this instance.

• connect_modify –

  Add a new connection or modify an existing one within the specified port of this instance.

• tie_port –

  Set a constant signal value for the specified port and bit index.

• has_tied_ports –

  Checks the ports of this instance whether any are tied to constant values.

• has_tied_inputs –

  Checks the input ports of this instance whether any are tied to constant values.

• has_tied_outputs –

  Checks the output ports of this instance whether any are tied to constant values.

• update_signedness –

  Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

• split –

  Performs a bit-wise split on this instance.

• p2v –

  Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

• ps2v –

  Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

• set –

  Sets the signal on a port.

Attributes:

• input_port (Port[Instance]) –

  The input port of the gate.

• y_width (PositiveInt) –

  Width of the gate, based on a certain port's width, depending on the actual gate.

• a_width (PositiveInt) –

  Width of the gate's A port.

• a_signed (bool) –

  The signedness of input port A.

• output_port (Port[Instance]) –

  The output port of the gate.

• truth_table (Dict[Signal, Signal]) –

  A simple truth table as a dictionary.

• name (str) –

  The name of the element.

• metadata (MetadataMixin) –

  Metadata of a netlist element.

• path (InstancePath) –

  Returns the InstancePath of the netlist element.

• type (EType) –

  The type of the element, which is an instance.

• hierarchy_level (int) –

  The level of hierarchy of the element in the design.

• has_parent (bool) –

  Whether this object has a parent.

• circuit ('Circuit') –

  The circuit object to which this netlist element belongs to.

• has_circuit (bool) –

  Whether this netlist element has a defined circuit it belongs to.

• locked (bool) –

  True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

• is_placeholder_instance (bool) –

  A placeholder represents an element that does not have a specific path.

• can_carry_signal (bool) –

  Whether this exact object is able to receive, pass or hold signal values.

• instance_type (str) –

  Identifier for instances of this gate type.

• connections (Dict[str, Dict[int, WireSegmentPath]]) –

  A dictionary mapping port names to their corresponding connection paths.

• connection_str_paths (Dict[str, Dict[int, str]]) –

  Returns a dictionary mapping port names to their corresponding connection paths as strings.

• ports (CustomDict[str, Port[Instance]]) –

  A dictionary mapping port names to their corresponding Port objects.

• input_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of input ports associated with this instance.

• output_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of output ports associated with this instance.

• has_unconnected_port_segments (bool) –

  Returns True if the instance has at least one unconnected port segment.

• signals (Dict[str, SignalArray]) –

  A dictionary with all signals currently present on all ports of this instance.

• is_blackbox (bool) –

  Flag indicating whether the instance represents neither a primitive element nor a module instance.

• b_width (PositiveInt) –

  Width of the gate's B port.

• is_combinational (bool) –

  Whether instances of this gate are considered combinational gates.

• is_sequential (bool) –

  Whether instances of this gate are considered sequential gates.

• data_width (int) –

  The data width of this instance.

input_port property

input_port: Port[Instance]

The input port of the gate.

y_width property

y_width: PositiveInt

Width of the gate, based on a certain port's width, depending on the actual gate.

a_width property

a_width: PositiveInt

Width of the gate's A port.

a_signed property

a_signed: bool

The signedness of input port A.

output_port property

output_port: Port[Instance]

The output port of the gate.

truth_table property

truth_table: Dict[Signal, Signal]

A simple truth table as a dictionary.

This dictionary contains the input-output mapping for unary gates that evaluate bitwise (e.g. Buffer, NotGate). Not implemented for arithmetic gates (e.g. NegGate, PosGate).

name instance-attribute

name: str

The name of the element.

!!! Do not modify this variable after instantiating it. Use NetlistElement.set_name() instead. Modifying this variable might lead to inconsistencies later on.

metadata class-attribute instance-attribute

metadata: MetadataMixin = MetadataMixin()

Metadata of a netlist element.

Can be user-defined, or e. g. by Yosys (such as src for the HDL source). Is also grouped by categories, i.e. all metadata from Yosys can be accessed via Module.metadata["yosys"], or via Module.metadata.yosys, which both return a dictionary of all metadata. Read the documentation of MetaDataMixin for more information.

path property

path: InstancePath

Returns the InstancePath of the netlist element.

The InstancePath object is constructed using the element's type and its raw hierarchical path.

Returns:

• InstancePath ( InstancePath ) –

  The hierarchical path of the netlist element.

type property

type: EType

The type of the element, which is an instance.

hierarchy_level property

hierarchy_level: int

The level of hierarchy of the element in the design.

The hierarchy level is the number of separators in the element's raw path. For example, a top-level instance has a hierarchy level of 0, while a direct submodule instance has a hierarchy level of 1.

Returns:

• int ( int ) –

  The hierarchy level of the element.

has_parent property

has_parent: bool

Whether this object has a parent.

circuit property

circuit: 'Circuit'

The circuit object to which this netlist element belongs to.

• For a module, returns the circuit to which the module belongs.
• For any other netlist element, recursively returns the circuit of the parent, which ultimately leads to a module, to which the netlist element belongs.

Raises:

• ParentNotFoundError –

  If a parent cannot be resolved somewhere in the hierarchical chain.

• ObjectNotFoundError –

  If for a module no circuit is set.

has_circuit property

has_circuit: bool

Whether this netlist element has a defined circuit it belongs to.

Tries to access self.circuit and returns whether the call was successful. Can be used instead of a try-except clause around the call to NetlistElement.circuit.

locked property

locked: bool

True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

Can be changed via NetlistElement.change_mutability(bool).

Immutability is used to prevent accidental changes to the design.

is_placeholder_instance property

is_placeholder_instance: bool

A placeholder represents an element that does not have a specific path.

True if this NetlistElement instance represents a placeholder, False otherwise.

can_carry_signal property

can_carry_signal: bool

Whether this exact object is able to receive, pass or hold signal values.

True for ports (as they drive or receive values) and wires (as they pass the signals from driver to load ports) as well as their respective segments. False for instances and modules.

instance_type class-attribute instance-attribute

instance_type: str = CFG.id_internal

Identifier for instances of this gate type.

connections property

connections: Dict[str, Dict[int, WireSegmentPath]]

A dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port. Elements with no connection (i.e. the path is None) are excluded. In case these are needed, use Instance.get_connections() instead.

Example

{ 'port1': {1: WireSegmentPath('path/to/element1'), 2: WireSegmentPath('path/to/element2')}, 'port2': {1: WireSegmentPath('path/to/element3')} }

connection_str_paths property

connection_str_paths: Dict[str, Dict[int, str]]

Returns a dictionary mapping port names to their corresponding connection paths as strings.

The keys are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are the raw string paths.

Example

{ 'port1': {0: 'path.to.element1', 1: 'path.to.element2'}, 'port2': {0: 'path.to.element3'} }

ports property

ports: CustomDict[str, Port[Instance]]

A dictionary mapping port names to their corresponding Port objects.

The keys of the dictionary are the names of the ports. The values are Port objects representing the ports.

Returns:

• CustomDict[str, Port[Instance]] –

  A dictionary mapping port names to their corresponding Port objects.

input_ports property

input_ports: Tuple[Port[Instance], ...]

Returns a tuple of input ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as inputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the input ports.

output_ports property

output_ports: Tuple[Port[Instance], ...]

Returns a tuple of output ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as outputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the output ports.

has_unconnected_port_segments property

has_unconnected_port_segments: bool

Returns True if the instance has at least one unconnected port segment.

signals property

signals: Dict[str, SignalArray]

A dictionary with all signals currently present on all ports of this instance.

is_blackbox property

is_blackbox: bool

Flag indicating whether the instance represents neither a primitive element nor a module instance.

If True, this instance does not have a module definition, and is also not a basic component (i.e. a primitive gate instance) from the internal gate library, such as a gate or flip-flop.

b_width property

b_width: PositiveInt

Width of the gate's B port.

is_combinational property

is_combinational: bool

Whether instances of this gate are considered combinational gates.

True for combinational gates, such as AND gates or arithmetic gates. False for flip-flops and latches.

is_sequential property

is_sequential: bool

Whether instances of this gate are considered sequential gates.

False for combinational gates, such as AND gates or arithmetic gates. True for flip-flops and latches.

data_width property

data_width: int

The data width of this instance.

Defaults to the data width of the output port. Can be overwritten in extended classes.

In contrast to self.width, which is used for the creation and initialization, this property is linked to the data width of the output port. This property is useful when the data width of the output port can be changed.

model_post_init

model_post_init(__context: object) -> None

Initializes the gate's ports and connections.

This method is called after the gate's attributes have been initialized, and it sets up the gate's ports and connections.

get_result

get_result(s: Signal) -> Signal

Returns the result of this gate's operation for given Signal s.

This method is only implemented for bitwise evaluating gates (e.g. Buffer, NotGate). This method raises an UnsupportedOperationError if used on arithmetic gates (e.g. PosGate, NegGate).

For vector-level operations on full signal arrays, use :meth:get_result_vector instead.

Parameters:

• s

  (Signal) –

  The Signal, i.e. the input operand.

Raises:

• UnsupportedOperationError –

  For gates that do not evaluate bitwise (e.g. arithmetic gates).

Returns:

• Signal ( Signal ) –

  The result of this gate's operation on the given signals.

get_result_vector

get_result_vector(s: SignalArray) -> SignalArray

Returns the result of this gate's operation for a full signal vector.

This method provides a unified interface for all unary gates to operate on :class:SignalArray (multi-bit) inputs. The default implementation iterates over each bit index and calls :meth:get_result for bitwise gates (e.g. Buffer, NotGate). Gates that operate on the full vector (e.g. arithmetic gates like PosGate, NegGate) override this method with their vector-level logic.

For reduction gates (e.g. ReduceAnd, ReduceOr), the output is a 1-bit :class:SignalArray regardless of input width.

Parameters:

• s

  (SignalArray) –

  The input signal array.

Returns:

• SignalArray ( SignalArray ) –

  The result of this gate's operation on the given signals. For bitwise gates, this has the same width as the input. For reduction gates, this is a 1-bit SignalArray.

signal_in

signal_in(idx: NonNegativeInt = 0) -> Signal

The input signal of the gate.

Returns:

• Signal ( Signal ) –

  The input signal of the gate.

signal_out

signal_out(idx: NonNegativeInt = 0) -> Signal

The output signal of the gate.

Returns:

• Signal ( Signal ) –

  The output signal of the gate.

change_mutability

change_mutability(is_now_locked: bool, recursive: bool = False) -> Self

Change the mutability status of this instance and optionally its ports.

This method allows setting whether this instance can be modified or not. If recursive is set to True, it also applies the same mutability status to all ports of this instance.

Parameters:

• is_now_locked

  (bool) –

  The new mutability status for this instance.

• recursive

  (bool, default: False ) –

  Whether to apply the change recursively to its ports. Defaults to False.

evaluate

evaluate() -> None

Evaluates the gate's output signal based on its input signals.

This method is called when the gate's input signals change, and it updates the gate's output signal accordingly.

all_connections

all_connections(
    include_unconnected: bool,
) -> Dict[str, Dict[int, WireSegmentPath]]

Returns a dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port.

Parameters:

• include_unconnected

  (bool) –

  Whether to include unconnected ports in the result.

Returns:

• Dict[str, Dict[int, WireSegmentPath]] –

  A dictionary mapping port names to their corresponding connection paths.

connect

connect(
    port_name: str,
    ws_path: Optional[WireSegmentPath],
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add connections to the specified port of this instance.

This method can establish multiple connections if a range of indices is provided.

Parameters:

• port_name

  (str) –

  The name of the port where the connection(s) should be established.

• ws_path

  (Optional[WireSegmentPath]) –

  The path of the wire segment that will be connected to this port. If None, the associated port (segment) remains unconnected.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

Raises:

• ObjectLockedError –

  If this instance is currently locked, and no connection can be made.

disconnect

disconnect(port_name: str, index: Optional[int] = None) -> None

Remove an existing connection from a specified port of this instance.

This method disconnects the wire segment at the given index within the specified port_name.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be removed.

• index

  (Optional[int], default: None ) –

  The bit index within the port for this disconnection. Defaults to None, which completely disconnects the port.

Raises:

• ObjectLockedError –

  If this instance is locked.

• ObjectNotFoundError –

  If no port exists with the given name.

get_connection

get_connection(
    port_name: str, index: Optional[NonNegativeInt] = None
) -> Union[WireSegmentPath, Dict[int, WireSegmentPath], None]

Retrieve the connection path associated with a specified port and bit index.

If index is provided, this method returns the wire segment path connected to that specific bit within the port. Otherwise, it returns all connections for the given port as a dictionary mapping indices to WireSegmentPaths.

Parameters:

• port_name

  (str) –

  The name of the port for which to retrieve the connection(s).

• index

  (Optional[NonNegativeInt], default: None ) –

  The bit index within the port. Defaults to None.

Returns:

• Union[WireSegmentPath, Dict[int, WireSegmentPath], None] –

  Union[WireSegmentPath, Dict[int, WireSegmentPath]]: Either a single WireSegmentPath or a dictionary mapping indices to WireSegmentPaths.

modify_connection

modify_connection(
    port_name: str, ws_path: WireSegmentPath, index: NonNegativeInt = 0
) -> None

Modify an existing connection within a specified port of this instance.

This method updates the wire segment path at the given index within the specified port_name. If the index does not exist yet, it is newly added, changing the width of the port.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be modified.

• ws_path

  (WireSegmentPath) –

  The new wire segment path for this connection.

• index

  (NonNegativeInt, default: 0 ) –

  The bit index within the port. Defaults to 0.

connect_modify

connect_modify(
    port_name: str,
    ws_path: WireSegmentPath,
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add a new connection or modify an existing one within the specified port of this instance.

If the connection already exists at the given index and port_name, it will be modified. Otherwise, a new connection is added.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be established or updated.

• ws_path

  (WireSegmentPath) –

  The path of the wire segment that will be connected to this port.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

tie_port

tie_port(name: str, index: NonNegativeInt, sig_value: LogicLevel) -> None

Set a constant signal value for the specified port and bit index.

If the specified port does not exist, an error message is logged and the function returns False. Otherwise, the method tries to set the constant signal value for that port and returns True if successful.

Does not work for instance output ports, as they are always driven by their parent instances.

Parameters:

• name

  (str) –

  The name of the port.

• index

  (NonNegativeInt) –

  The bit index within the port.

• sig_value

  (LogicLevel) –

  The constant signal value to be set ('0', '1', or 'Z').

Raises:

• ObjectNotFoundError –

  If no such port or port segment exists.

• AlreadyConnectedError –

  (raised by: PortSegment.tie_signal) If this segment is belongs to a load port and is already connected to a wire, from which it receives its value.

• InvalidDirectionError –

  (raised by: PortSegment.tie_signal) If this port segment belongs to an instance output port, which is driven by the instance inputs and the instance's internal logic.

• InvalidSignalError –

  (raised by: PortSegment.tie_signal) If an invalid value is provided.

has_tied_ports

has_tied_ports() -> bool

Checks the ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any ports of this instance are tied to constant values. False otherwise, i.e. all ports are connected to wires.

has_tied_inputs

has_tied_inputs() -> bool

Checks the input ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any input ports of this instance are tied to constant values. False otherwise, i.e. all input ports are connected to wires.

has_tied_outputs

has_tied_outputs() -> bool

Checks the output ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any output ports of this instance are tied to constant values. False otherwise, i.e. all output ports are connected to wires.

update_signedness

update_signedness(port_name: str) -> None

Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

Parameters:

• port_name

  (str) –

  The name of the port, of which the signedness value is retrieved.

split

split() -> Dict[NonNegativeInt, Self]

Performs a bit-wise split on this instance.

If this instance supports splitting and has a data width of n bit, this method splits this instance into n 1-bit instances. This works for instances, where each output bit depends only on the corresponding input bit(s), e.g. an AND gate or a D-Flipflop.

Returns:

• Dict[NonNegativeInt, Self] –

  Dict[int, Instance]: An n-bit large dictionary, where each key conforms to a bit of the original instance, and each value is an 1-bit instance representing the corresponding "slice" of the original instance.

Raises:

• SplittingUnsupportedError –

  If this instance does not support splitting. Happens for any gate or instance whose behavior depends on the whole bus, and splitting would make it lose its meaning.

p2v

p2v(
    port: ANY_PORT,
    exclude_indices: Optional[List[int]] = None,
    include_indices: Optional[List[int]] = None,
) -> str

Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a Port object and converts them to their corresponding Verilog signal structure (p2v -> Port to Verilog signal syntax). For each segment of the port, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port is set to a constant, the corresponding constant wire segment placeholder is used instead. Port segments can be excluded from the conversion by providing a list of indices to the exclude_indices parameter, indicating which segments should be excluded from the conversion (e.g. segments that are known to be unconnected). Vice versa, only a certain subset of the port's segments may be converted to Verilog syntax, if include_indices is a given list of port indices. All indices not present in the list will be excluded from the conversion.

Parameters:

• port

  (Port) –

  The Port object to convert.

• exclude_indices

  (List[int], default: None ) –

  A list of indices to exclude from the conversion. Defaults to None.

• include_indices

  (List[int], default: None ) –

  A list of indices (i.e. port slices) to include only for the conversion. Defaults to None.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

ps2v

ps2v(ps_dict: Dict[int, PortSegment]) -> str

Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a PortSegment dictionary and converts them to their corresponding Verilog signal structure (ps2v -> PortSegment to Verilog signal syntax). For each segment, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port segment is set to a constant, the corresponding constant wire segment placeholder is used instead.

Parameters:

• ps_dict

  (Dict[int, PortSegment]) –

  The PortSegment dictionary to convert. Each key (int) conforms to the index of the associated PortSegment object.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

• UnsupportedOperationError –

  If two segments belong to different modules.

set

set(
    port_name: str,
    new_signal: SignalOrLogicLevel,
    idx: Union[int, List[int]] = 0,
) -> None

Sets the signal on a port.

Parameters:

• port_name

  (str) –

  The name of the port to set the signal on.

• new_signal

  (Signal) –

  The new signal value.

• idx

  (Union[int, List[int]], default: 0 ) –

  The index (or indices) to apply the given signal to. Can either be an integer (single index to set) or an iterable of integers (e.g. a list of indices). For every integer of the iterable the signal value of the corresponding port index is set to the given new_signal. Defaults to 0.

Example

from netlist_carpentry.utils.gate_factory import and_gate module = Module(name='m') a = module.create_port('a', 'input', width=6) instance = and_gate(module, 'inst', A=a)

This sets the value of bit 0 of port A to HIGH

instance.set('A', 1, 0) instance.ports['A'].signal_str 'xxxxx1'

This sets the value of bits 1, 3 and 5 of port A to LOW, leaving the other bits as they already are.

instance.set('A', 0, [1, 3, 5]) instance.ports['A'].signal_str '0x0x01'

ReduceGate

Bases: _Out1BitMixin, UnaryGate

A base class for reduce gates.

Reduce gates are gates that have an n-bit input signal, and they produce a 1-bit output signal by performing a given reducing operation. This class provides a common interface for all reduce gates, including methods for evaluating the gate's output and setting its output signal.

Methods:

• model_post_init –

  Initializes the gate's ports and connections.

• signal_out –

  The output signal of the gate.

• get_result_vector –

  Returns the result of this reduction gate's operation for a full signal vector.

• change_mutability –

  Change the mutability status of this instance and optionally its ports.

• evaluate –

  Evaluates the gate's output signal based on its input signals.

• all_connections –

  Returns a dictionary mapping port names to their corresponding connection paths.

• connect –

  Add connections to the specified port of this instance.

• disconnect –

  Remove an existing connection from a specified port of this instance.

• get_connection –

  Retrieve the connection path associated with a specified port and bit index.

• modify_connection –

  Modify an existing connection within a specified port of this instance.

• connect_modify –

  Add a new connection or modify an existing one within the specified port of this instance.

• tie_port –

  Set a constant signal value for the specified port and bit index.

• has_tied_ports –

  Checks the ports of this instance whether any are tied to constant values.

• has_tied_inputs –

  Checks the input ports of this instance whether any are tied to constant values.

• has_tied_outputs –

  Checks the output ports of this instance whether any are tied to constant values.

• update_signedness –

  Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

• split –

  Performs a bit-wise split on this instance.

• p2v –

  Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

• ps2v –

  Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

• set –

  Sets the signal on a port.

• get_result –

  Returns the result of this gate's operation for given Signal s.

• signal_in –

  The input signal of the gate.

Attributes:

• reduce_operation (Callable[[Signal, Signal], Signal]) –

  Provides a lambda function for this gate.

• name (str) –

  The name of the element.

• metadata (MetadataMixin) –

  Metadata of a netlist element.

• path (InstancePath) –

  Returns the InstancePath of the netlist element.

• type (EType) –

  The type of the element, which is an instance.

• hierarchy_level (int) –

  The level of hierarchy of the element in the design.

• has_parent (bool) –

  Whether this object has a parent.

• circuit ('Circuit') –

  The circuit object to which this netlist element belongs to.

• has_circuit (bool) –

  Whether this netlist element has a defined circuit it belongs to.

• locked (bool) –

  True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

• is_placeholder_instance (bool) –

  A placeholder represents an element that does not have a specific path.

• can_carry_signal (bool) –

  Whether this exact object is able to receive, pass or hold signal values.

• instance_type (str) –

  Identifier for instances of this gate type.

• connections (Dict[str, Dict[int, WireSegmentPath]]) –

  A dictionary mapping port names to their corresponding connection paths.

• connection_str_paths (Dict[str, Dict[int, str]]) –

  Returns a dictionary mapping port names to their corresponding connection paths as strings.

• ports (CustomDict[str, Port[Instance]]) –

  A dictionary mapping port names to their corresponding Port objects.

• input_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of input ports associated with this instance.

• output_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of output ports associated with this instance.

• has_unconnected_port_segments (bool) –

  Returns True if the instance has at least one unconnected port segment.

• signals (Dict[str, SignalArray]) –

  A dictionary with all signals currently present on all ports of this instance.

• is_blackbox (bool) –

  Flag indicating whether the instance represents neither a primitive element nor a module instance.

• y_width (PositiveInt) –

  Width of the gate, which is always 1 for gates that reduce N-bit inputs to 1 bit.

• a_width (PositiveInt) –

  Width of the gate's A port.

• b_width (PositiveInt) –

  Width of the gate's B port.

• is_combinational (bool) –

  Whether instances of this gate are considered combinational gates.

• is_sequential (bool) –

  Whether instances of this gate are considered sequential gates.

• output_port (Port[Instance]) –

  The output port of the gate.

• data_width (int) –

  The data width of this instance.

• input_port (Port[Instance]) –

  The input port of the gate.

• a_signed (bool) –

  The signedness of input port A.

• truth_table (Dict[Signal, Signal]) –

  A simple truth table as a dictionary.

reduce_operation property

reduce_operation: Callable[[Signal, Signal], Signal]

Provides a lambda function for this gate.

The lambda function takes two signals and executes this gate's operation on both of them. In junction with functools.reduce(), this reduces the input signal array down to a single bit by concatenating the operation of this gate bit-by-bit.

name instance-attribute

name: str

The name of the element.

!!! Do not modify this variable after instantiating it. Use NetlistElement.set_name() instead. Modifying this variable might lead to inconsistencies later on.

metadata class-attribute instance-attribute

metadata: MetadataMixin = MetadataMixin()

Metadata of a netlist element.

Can be user-defined, or e. g. by Yosys (such as src for the HDL source). Is also grouped by categories, i.e. all metadata from Yosys can be accessed via Module.metadata["yosys"], or via Module.metadata.yosys, which both return a dictionary of all metadata. Read the documentation of MetaDataMixin for more information.

path property

path: InstancePath

Returns the InstancePath of the netlist element.

The InstancePath object is constructed using the element's type and its raw hierarchical path.

Returns:

• InstancePath ( InstancePath ) –

  The hierarchical path of the netlist element.

type property

type: EType

The type of the element, which is an instance.

hierarchy_level property

hierarchy_level: int

The level of hierarchy of the element in the design.

The hierarchy level is the number of separators in the element's raw path. For example, a top-level instance has a hierarchy level of 0, while a direct submodule instance has a hierarchy level of 1.

Returns:

• int ( int ) –

  The hierarchy level of the element.

has_parent property

has_parent: bool

Whether this object has a parent.

circuit property

circuit: 'Circuit'

The circuit object to which this netlist element belongs to.

• For a module, returns the circuit to which the module belongs.
• For any other netlist element, recursively returns the circuit of the parent, which ultimately leads to a module, to which the netlist element belongs.

Raises:

• ParentNotFoundError –

  If a parent cannot be resolved somewhere in the hierarchical chain.

• ObjectNotFoundError –

  If for a module no circuit is set.

has_circuit property

has_circuit: bool

Whether this netlist element has a defined circuit it belongs to.

Tries to access self.circuit and returns whether the call was successful. Can be used instead of a try-except clause around the call to NetlistElement.circuit.

locked property

locked: bool

True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

Can be changed via NetlistElement.change_mutability(bool).

Immutability is used to prevent accidental changes to the design.

is_placeholder_instance property

is_placeholder_instance: bool

A placeholder represents an element that does not have a specific path.

True if this NetlistElement instance represents a placeholder, False otherwise.

can_carry_signal property

can_carry_signal: bool

Whether this exact object is able to receive, pass or hold signal values.

True for ports (as they drive or receive values) and wires (as they pass the signals from driver to load ports) as well as their respective segments. False for instances and modules.

instance_type class-attribute instance-attribute

instance_type: str = CFG.id_internal

Identifier for instances of this gate type.

connections property

connections: Dict[str, Dict[int, WireSegmentPath]]

A dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port. Elements with no connection (i.e. the path is None) are excluded. In case these are needed, use Instance.get_connections() instead.

Example

{ 'port1': {1: WireSegmentPath('path/to/element1'), 2: WireSegmentPath('path/to/element2')}, 'port2': {1: WireSegmentPath('path/to/element3')} }

connection_str_paths property

connection_str_paths: Dict[str, Dict[int, str]]

Returns a dictionary mapping port names to their corresponding connection paths as strings.

The keys are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are the raw string paths.

Example

{ 'port1': {0: 'path.to.element1', 1: 'path.to.element2'}, 'port2': {0: 'path.to.element3'} }

ports property

ports: CustomDict[str, Port[Instance]]

A dictionary mapping port names to their corresponding Port objects.

The keys of the dictionary are the names of the ports. The values are Port objects representing the ports.

Returns:

• CustomDict[str, Port[Instance]] –

  A dictionary mapping port names to their corresponding Port objects.

input_ports property

input_ports: Tuple[Port[Instance], ...]

Returns a tuple of input ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as inputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the input ports.

output_ports property

output_ports: Tuple[Port[Instance], ...]

Returns a tuple of output ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as outputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the output ports.

has_unconnected_port_segments property

has_unconnected_port_segments: bool

Returns True if the instance has at least one unconnected port segment.

signals property

signals: Dict[str, SignalArray]

A dictionary with all signals currently present on all ports of this instance.

is_blackbox property

is_blackbox: bool

Flag indicating whether the instance represents neither a primitive element nor a module instance.

If True, this instance does not have a module definition, and is also not a basic component (i.e. a primitive gate instance) from the internal gate library, such as a gate or flip-flop.

y_width property

y_width: PositiveInt

Width of the gate, which is always 1 for gates that reduce N-bit inputs to 1 bit.

a_width property

a_width: PositiveInt

Width of the gate's A port.

b_width property

b_width: PositiveInt

Width of the gate's B port.

is_combinational property

is_combinational: bool

Whether instances of this gate are considered combinational gates.

True for combinational gates, such as AND gates or arithmetic gates. False for flip-flops and latches.

is_sequential property

is_sequential: bool

Whether instances of this gate are considered sequential gates.

False for combinational gates, such as AND gates or arithmetic gates. True for flip-flops and latches.

output_port property

output_port: Port[Instance]

The output port of the gate.

data_width property

data_width: int

The data width of this instance.

Defaults to the data width of the output port. Can be overwritten in extended classes.

In contrast to self.width, which is used for the creation and initialization, this property is linked to the data width of the output port. This property is useful when the data width of the output port can be changed.

input_port property

input_port: Port[Instance]

The input port of the gate.

a_signed property

a_signed: bool

The signedness of input port A.

truth_table property

truth_table: Dict[Signal, Signal]

A simple truth table as a dictionary.

This dictionary contains the input-output mapping for unary gates that evaluate bitwise (e.g. Buffer, NotGate). Not implemented for arithmetic gates (e.g. NegGate, PosGate).

model_post_init

model_post_init(__context: object) -> None

Initializes the gate's ports and connections.

This method is called after the gate's attributes have been initialized, and it sets up the gate's ports and connections.

signal_out

signal_out() -> Signal

The output signal of the gate.

get_result_vector

get_result_vector(s: SignalArray) -> SignalArray

Returns the result of this reduction gate's operation for a full signal vector.

Reduces an N-bit :class:SignalArray to a 1-bit :class:SignalArray by applying :meth:reduce_operation across all bits using :func:functools.reduce.

Parameters:

• s

  (SignalArray) –

  The input signal array of any width.

Returns:

• SignalArray ( SignalArray ) –

  A 1-bit SignalArray containing the reduction result.

change_mutability

change_mutability(is_now_locked: bool, recursive: bool = False) -> Self

Change the mutability status of this instance and optionally its ports.

This method allows setting whether this instance can be modified or not. If recursive is set to True, it also applies the same mutability status to all ports of this instance.

Parameters:

• is_now_locked

  (bool) –

  The new mutability status for this instance.

• recursive

  (bool, default: False ) –

  Whether to apply the change recursively to its ports. Defaults to False.

evaluate

evaluate() -> None

Evaluates the gate's output signal based on its input signals.

This method is called when the gate's input signals change, and it updates the gate's output signal accordingly.

all_connections

all_connections(
    include_unconnected: bool,
) -> Dict[str, Dict[int, WireSegmentPath]]

Returns a dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port.

Parameters:

• include_unconnected

  (bool) –

  Whether to include unconnected ports in the result.

Returns:

• Dict[str, Dict[int, WireSegmentPath]] –

  A dictionary mapping port names to their corresponding connection paths.

connect

connect(
    port_name: str,
    ws_path: Optional[WireSegmentPath],
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add connections to the specified port of this instance.

This method can establish multiple connections if a range of indices is provided.

Parameters:

• port_name

  (str) –

  The name of the port where the connection(s) should be established.

• ws_path

  (Optional[WireSegmentPath]) –

  The path of the wire segment that will be connected to this port. If None, the associated port (segment) remains unconnected.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

Raises:

• ObjectLockedError –

  If this instance is currently locked, and no connection can be made.

disconnect

disconnect(port_name: str, index: Optional[int] = None) -> None

Remove an existing connection from a specified port of this instance.

This method disconnects the wire segment at the given index within the specified port_name.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be removed.

• index

  (Optional[int], default: None ) –

  The bit index within the port for this disconnection. Defaults to None, which completely disconnects the port.

Raises:

• ObjectLockedError –

  If this instance is locked.

• ObjectNotFoundError –

  If no port exists with the given name.

get_connection

get_connection(
    port_name: str, index: Optional[NonNegativeInt] = None
) -> Union[WireSegmentPath, Dict[int, WireSegmentPath], None]

Retrieve the connection path associated with a specified port and bit index.

If index is provided, this method returns the wire segment path connected to that specific bit within the port. Otherwise, it returns all connections for the given port as a dictionary mapping indices to WireSegmentPaths.

Parameters:

• port_name

  (str) –

  The name of the port for which to retrieve the connection(s).

• index

  (Optional[NonNegativeInt], default: None ) –

  The bit index within the port. Defaults to None.

Returns:

• Union[WireSegmentPath, Dict[int, WireSegmentPath], None] –

  Union[WireSegmentPath, Dict[int, WireSegmentPath]]: Either a single WireSegmentPath or a dictionary mapping indices to WireSegmentPaths.

modify_connection

modify_connection(
    port_name: str, ws_path: WireSegmentPath, index: NonNegativeInt = 0
) -> None

Modify an existing connection within a specified port of this instance.

This method updates the wire segment path at the given index within the specified port_name. If the index does not exist yet, it is newly added, changing the width of the port.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be modified.

• ws_path

  (WireSegmentPath) –

  The new wire segment path for this connection.

• index

  (NonNegativeInt, default: 0 ) –

  The bit index within the port. Defaults to 0.

connect_modify

connect_modify(
    port_name: str,
    ws_path: WireSegmentPath,
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add a new connection or modify an existing one within the specified port of this instance.

If the connection already exists at the given index and port_name, it will be modified. Otherwise, a new connection is added.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be established or updated.

• ws_path

  (WireSegmentPath) –

  The path of the wire segment that will be connected to this port.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

tie_port

tie_port(name: str, index: NonNegativeInt, sig_value: LogicLevel) -> None

Set a constant signal value for the specified port and bit index.

If the specified port does not exist, an error message is logged and the function returns False. Otherwise, the method tries to set the constant signal value for that port and returns True if successful.

Does not work for instance output ports, as they are always driven by their parent instances.

Parameters:

• name

  (str) –

  The name of the port.

• index

  (NonNegativeInt) –

  The bit index within the port.

• sig_value

  (LogicLevel) –

  The constant signal value to be set ('0', '1', or 'Z').

Raises:

• ObjectNotFoundError –

  If no such port or port segment exists.

• AlreadyConnectedError –

  (raised by: PortSegment.tie_signal) If this segment is belongs to a load port and is already connected to a wire, from which it receives its value.

• InvalidDirectionError –

  (raised by: PortSegment.tie_signal) If this port segment belongs to an instance output port, which is driven by the instance inputs and the instance's internal logic.

• InvalidSignalError –

  (raised by: PortSegment.tie_signal) If an invalid value is provided.

has_tied_ports

has_tied_ports() -> bool

Checks the ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any ports of this instance are tied to constant values. False otherwise, i.e. all ports are connected to wires.

has_tied_inputs

has_tied_inputs() -> bool

Checks the input ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any input ports of this instance are tied to constant values. False otherwise, i.e. all input ports are connected to wires.

has_tied_outputs

has_tied_outputs() -> bool

Checks the output ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any output ports of this instance are tied to constant values. False otherwise, i.e. all output ports are connected to wires.

update_signedness

update_signedness(port_name: str) -> None

Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

Parameters:

• port_name

  (str) –

  The name of the port, of which the signedness value is retrieved.

split

split() -> Dict[NonNegativeInt, Self]

Performs a bit-wise split on this instance.

If this instance supports splitting and has a data width of n bit, this method splits this instance into n 1-bit instances. This works for instances, where each output bit depends only on the corresponding input bit(s), e.g. an AND gate or a D-Flipflop.

Returns:

• Dict[NonNegativeInt, Self] –

  Dict[int, Instance]: An n-bit large dictionary, where each key conforms to a bit of the original instance, and each value is an 1-bit instance representing the corresponding "slice" of the original instance.

Raises:

• SplittingUnsupportedError –

  If this instance does not support splitting. Happens for any gate or instance whose behavior depends on the whole bus, and splitting would make it lose its meaning.

p2v

p2v(
    port: ANY_PORT,
    exclude_indices: Optional[List[int]] = None,
    include_indices: Optional[List[int]] = None,
) -> str

Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a Port object and converts them to their corresponding Verilog signal structure (p2v -> Port to Verilog signal syntax). For each segment of the port, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port is set to a constant, the corresponding constant wire segment placeholder is used instead. Port segments can be excluded from the conversion by providing a list of indices to the exclude_indices parameter, indicating which segments should be excluded from the conversion (e.g. segments that are known to be unconnected). Vice versa, only a certain subset of the port's segments may be converted to Verilog syntax, if include_indices is a given list of port indices. All indices not present in the list will be excluded from the conversion.

Parameters:

• port

  (Port) –

  The Port object to convert.

• exclude_indices

  (List[int], default: None ) –

  A list of indices to exclude from the conversion. Defaults to None.

• include_indices

  (List[int], default: None ) –

  A list of indices (i.e. port slices) to include only for the conversion. Defaults to None.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

ps2v

ps2v(ps_dict: Dict[int, PortSegment]) -> str

Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a PortSegment dictionary and converts them to their corresponding Verilog signal structure (ps2v -> PortSegment to Verilog signal syntax). For each segment, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port segment is set to a constant, the corresponding constant wire segment placeholder is used instead.

Parameters:

• ps_dict

  (Dict[int, PortSegment]) –

  The PortSegment dictionary to convert. Each key (int) conforms to the index of the associated PortSegment object.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

• UnsupportedOperationError –

  If two segments belong to different modules.

set

set(
    port_name: str,
    new_signal: SignalOrLogicLevel,
    idx: Union[int, List[int]] = 0,
) -> None

Sets the signal on a port.

Parameters:

• port_name

  (str) –

  The name of the port to set the signal on.

• new_signal

  (Signal) –

  The new signal value.

• idx

  (Union[int, List[int]], default: 0 ) –

  The index (or indices) to apply the given signal to. Can either be an integer (single index to set) or an iterable of integers (e.g. a list of indices). For every integer of the iterable the signal value of the corresponding port index is set to the given new_signal. Defaults to 0.

Example

from netlist_carpentry.utils.gate_factory import and_gate module = Module(name='m') a = module.create_port('a', 'input', width=6) instance = and_gate(module, 'inst', A=a)

This sets the value of bit 0 of port A to HIGH

instance.set('A', 1, 0) instance.ports['A'].signal_str 'xxxxx1'

This sets the value of bits 1, 3 and 5 of port A to LOW, leaving the other bits as they already are.

instance.set('A', 0, [1, 3, 5]) instance.ports['A'].signal_str '0x0x01'

get_result

get_result(s: Signal) -> Signal

Returns the result of this gate's operation for given Signal s.

This method is only implemented for bitwise evaluating gates (e.g. Buffer, NotGate). This method raises an UnsupportedOperationError if used on arithmetic gates (e.g. PosGate, NegGate).

For vector-level operations on full signal arrays, use :meth:get_result_vector instead.

Parameters:

• s

  (Signal) –

  The Signal, i.e. the input operand.

Raises:

• UnsupportedOperationError –

  For gates that do not evaluate bitwise (e.g. arithmetic gates).

Returns:

• Signal ( Signal ) –

  The result of this gate's operation on the given signals.

signal_in

signal_in(idx: NonNegativeInt = 0) -> Signal

The input signal of the gate.

Returns:

• Signal ( Signal ) –

  The input signal of the gate.

BinaryGate

Bases: PrimitiveGate, BaseModel

A base class for binary gates.

Binary gates are gates that have two input signals, and they produce a single output signal. This class provides a common interface for all binary gates, including methods for evaluating the gate's output and setting its output signal.

Methods:

• model_post_init –

  Initializes the gate's ports and connections.

• get_result –

  Returns the result of this gate's operation for given Signals s1 and s2.

• get_result_vector –

  Returns the result of this gate's operation for full signal vectors.

• signals_in –

  The input signals of the gate.

• signal_out –

  The output signal of the gate.

• change_mutability –

  Change the mutability status of this instance and optionally its ports.

• evaluate –

  Evaluates the gate's output signal based on its input signals.

• all_connections –

  Returns a dictionary mapping port names to their corresponding connection paths.

• connect –

  Add connections to the specified port of this instance.

• disconnect –

  Remove an existing connection from a specified port of this instance.

• get_connection –

  Retrieve the connection path associated with a specified port and bit index.

• modify_connection –

  Modify an existing connection within a specified port of this instance.

• connect_modify –

  Add a new connection or modify an existing one within the specified port of this instance.

• tie_port –

  Set a constant signal value for the specified port and bit index.

• has_tied_ports –

  Checks the ports of this instance whether any are tied to constant values.

• has_tied_inputs –

  Checks the input ports of this instance whether any are tied to constant values.

• has_tied_outputs –

  Checks the output ports of this instance whether any are tied to constant values.

• update_signedness –

  Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

• split –

  Performs a bit-wise split on this instance.

• p2v –

  Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

• ps2v –

  Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

• set –

  Sets the signal on a port.

Attributes:

• input_ports (Tuple[Port[Instance], Port[Instance]]) –

  The input ports of the gate as a 2-tuple.

• y_width (PositiveInt) –

  Width of the gate, based on a certain port's width, depending on the actual gate.

• a_width (PositiveInt) –

  Width of the gate's A port.

• a_signed (bool) –

  The signedness of input port A.

• b_width (PositiveInt) –

  Width of the gate's B port.

• b_signed (bool) –

  The signedness of input port B.

• output_port (Port[Instance]) –

  The output port of the gate.

• truth_table (Dict[Tuple[Signal, Signal], Signal]) –

  A simple truth table as a dictionary.

• name (str) –

  The name of the element.

• metadata (MetadataMixin) –

  Metadata of a netlist element.

• path (InstancePath) –

  Returns the InstancePath of the netlist element.

• type (EType) –

  The type of the element, which is an instance.

• hierarchy_level (int) –

  The level of hierarchy of the element in the design.

• has_parent (bool) –

  Whether this object has a parent.

• circuit ('Circuit') –

  The circuit object to which this netlist element belongs to.

• has_circuit (bool) –

  Whether this netlist element has a defined circuit it belongs to.

• locked (bool) –

  True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

• is_placeholder_instance (bool) –

  A placeholder represents an element that does not have a specific path.

• can_carry_signal (bool) –

  Whether this exact object is able to receive, pass or hold signal values.

• instance_type (str) –

  Identifier for instances of this gate type.

• connections (Dict[str, Dict[int, WireSegmentPath]]) –

  A dictionary mapping port names to their corresponding connection paths.

• connection_str_paths (Dict[str, Dict[int, str]]) –

  Returns a dictionary mapping port names to their corresponding connection paths as strings.

• ports (CustomDict[str, Port[Instance]]) –

  A dictionary mapping port names to their corresponding Port objects.

• output_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of output ports associated with this instance.

• has_unconnected_port_segments (bool) –

  Returns True if the instance has at least one unconnected port segment.

• signals (Dict[str, SignalArray]) –

  A dictionary with all signals currently present on all ports of this instance.

• is_blackbox (bool) –

  Flag indicating whether the instance represents neither a primitive element nor a module instance.

• is_combinational (bool) –

  Whether instances of this gate are considered combinational gates.

• is_sequential (bool) –

  Whether instances of this gate are considered sequential gates.

• data_width (int) –

  The data width of this instance.

input_ports property

input_ports: Tuple[Port[Instance], Port[Instance]]

The input ports of the gate as a 2-tuple.

y_width property

y_width: PositiveInt

Width of the gate, based on a certain port's width, depending on the actual gate.

a_width property

a_width: PositiveInt

Width of the gate's A port.

a_signed property

a_signed: bool

The signedness of input port A.

b_width property

b_width: PositiveInt

Width of the gate's B port.

b_signed property

b_signed: bool

The signedness of input port B.

output_port property

output_port: Port[Instance]

The output port of the gate.

truth_table property

truth_table: Dict[Tuple[Signal, Signal], Signal]

A simple truth table as a dictionary.

This dictionary contains the input-output mapping for unary gates that evaluate bitwise (e.g. AndGate, OrGate). Not implemented for arithmetic gates (e.g. Adder).

name instance-attribute

name: str

The name of the element.

!!! Do not modify this variable after instantiating it. Use NetlistElement.set_name() instead. Modifying this variable might lead to inconsistencies later on.

metadata class-attribute instance-attribute

metadata: MetadataMixin = MetadataMixin()

Metadata of a netlist element.

Can be user-defined, or e. g. by Yosys (such as src for the HDL source). Is also grouped by categories, i.e. all metadata from Yosys can be accessed via Module.metadata["yosys"], or via Module.metadata.yosys, which both return a dictionary of all metadata. Read the documentation of MetaDataMixin for more information.

path property

path: InstancePath

Returns the InstancePath of the netlist element.

The InstancePath object is constructed using the element's type and its raw hierarchical path.

Returns:

• InstancePath ( InstancePath ) –

  The hierarchical path of the netlist element.

type property

type: EType

The type of the element, which is an instance.

hierarchy_level property

hierarchy_level: int

The level of hierarchy of the element in the design.

The hierarchy level is the number of separators in the element's raw path. For example, a top-level instance has a hierarchy level of 0, while a direct submodule instance has a hierarchy level of 1.

Returns:

• int ( int ) –

  The hierarchy level of the element.

has_parent property

has_parent: bool

Whether this object has a parent.

circuit property

circuit: 'Circuit'

The circuit object to which this netlist element belongs to.

• For a module, returns the circuit to which the module belongs.
• For any other netlist element, recursively returns the circuit of the parent, which ultimately leads to a module, to which the netlist element belongs.

Raises:

• ParentNotFoundError –

  If a parent cannot be resolved somewhere in the hierarchical chain.

• ObjectNotFoundError –

  If for a module no circuit is set.

has_circuit property

has_circuit: bool

Whether this netlist element has a defined circuit it belongs to.

Tries to access self.circuit and returns whether the call was successful. Can be used instead of a try-except clause around the call to NetlistElement.circuit.

locked property

locked: bool

True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

Can be changed via NetlistElement.change_mutability(bool).

Immutability is used to prevent accidental changes to the design.

is_placeholder_instance property

is_placeholder_instance: bool

A placeholder represents an element that does not have a specific path.

True if this NetlistElement instance represents a placeholder, False otherwise.

can_carry_signal property

can_carry_signal: bool

Whether this exact object is able to receive, pass or hold signal values.

True for ports (as they drive or receive values) and wires (as they pass the signals from driver to load ports) as well as their respective segments. False for instances and modules.

instance_type class-attribute instance-attribute

instance_type: str = CFG.id_internal

Identifier for instances of this gate type.

connections property

connections: Dict[str, Dict[int, WireSegmentPath]]

A dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port. Elements with no connection (i.e. the path is None) are excluded. In case these are needed, use Instance.get_connections() instead.

Example

{ 'port1': {1: WireSegmentPath('path/to/element1'), 2: WireSegmentPath('path/to/element2')}, 'port2': {1: WireSegmentPath('path/to/element3')} }

connection_str_paths property

connection_str_paths: Dict[str, Dict[int, str]]

Returns a dictionary mapping port names to their corresponding connection paths as strings.

The keys are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are the raw string paths.

Example

{ 'port1': {0: 'path.to.element1', 1: 'path.to.element2'}, 'port2': {0: 'path.to.element3'} }

ports property

ports: CustomDict[str, Port[Instance]]

A dictionary mapping port names to their corresponding Port objects.

The keys of the dictionary are the names of the ports. The values are Port objects representing the ports.

Returns:

• CustomDict[str, Port[Instance]] –

  A dictionary mapping port names to their corresponding Port objects.

output_ports property

output_ports: Tuple[Port[Instance], ...]

Returns a tuple of output ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as outputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the output ports.

has_unconnected_port_segments property

has_unconnected_port_segments: bool

Returns True if the instance has at least one unconnected port segment.

signals property

signals: Dict[str, SignalArray]

A dictionary with all signals currently present on all ports of this instance.

is_blackbox property

is_blackbox: bool

Flag indicating whether the instance represents neither a primitive element nor a module instance.

If True, this instance does not have a module definition, and is also not a basic component (i.e. a primitive gate instance) from the internal gate library, such as a gate or flip-flop.

is_combinational property

is_combinational: bool

Whether instances of this gate are considered combinational gates.

True for combinational gates, such as AND gates or arithmetic gates. False for flip-flops and latches.

is_sequential property

is_sequential: bool

Whether instances of this gate are considered sequential gates.

False for combinational gates, such as AND gates or arithmetic gates. True for flip-flops and latches.

data_width property

data_width: int

The data width of this instance.

Defaults to the data width of the output port. Can be overwritten in extended classes.

In contrast to self.width, which is used for the creation and initialization, this property is linked to the data width of the output port. This property is useful when the data width of the output port can be changed.

model_post_init

model_post_init(__context: object) -> None

Initializes the gate's ports and connections.

This method is called after the gate's attributes have been initialized, and it sets up the gate's ports and connections.

get_result

get_result(s1: Signal, s2: Signal) -> Signal

Returns the result of this gate's operation for given Signals s1 and s2.

This method is only implemented for bitwise evaluating gates (e.g. AndGate, OrGate). This method raises an UnsupportedOperationError if used on other gates (e.g. Adder).

For vector-level operations on full signal arrays, use :meth:get_result_vector instead.

Parameters:

• s1

  (Signal) –

  The first Signal, i.e. the first operand.

• s2

  (Signal) –

  The second Signal, i.e. the second operand.

Raises:

• UnsupportedOperationError –

  For gates that do not evaluate bitwise (e.g. arithmetic gates).

Returns:

• Signal ( Signal ) –

  The result of this gate's operation on the given signals.

get_result_vector

get_result_vector(s1: SignalArray, s2: SignalArray) -> SignalArray

Returns the result of this gate's operation for full signal vectors.

This method provides a unified interface for all binary gates to operate on :class:SignalArray (multi-bit) inputs. The default implementation iterates over each bit index and calls :meth:get_result for bitwise gates (e.g. AndGate, OrGate, XorGate). Gates that operate on the full vectors (e.g. arithmetic gates like Adder, Subtractor, or comparison gates like LessThan) override this method with their vector-level logic.

For comparison gates that produce a single bit from two N-bit inputs (e.g. LessThan, Equal), the output is a 1-bit :class:SignalArray.

Parameters:

• s1

  (SignalArray) –

  The first input signal array.

• s2

  (SignalArray) –

  The second input signal array.

Returns:

• SignalArray ( SignalArray ) –

  The result of this gate's operation on the given signals. For bitwise gates, this has the same width as the inputs. For comparison/reduction gates, this is a 1-bit SignalArray.

signals_in

signals_in(idx: NonNegativeInt = 0) -> Tuple[Signal, Signal]

The input signals of the gate.

Returns:

• Tuple[Signal, Signal] –

  Tuple[Signal, Signal]: The input signals of the gate.

signal_out

signal_out(idx: NonNegativeInt = 0) -> Signal

The output signal of the gate.

Returns:

• Signal ( Signal ) –

  The output signal of the gate.

change_mutability

change_mutability(is_now_locked: bool, recursive: bool = False) -> Self

Change the mutability status of this instance and optionally its ports.

This method allows setting whether this instance can be modified or not. If recursive is set to True, it also applies the same mutability status to all ports of this instance.

Parameters:

• is_now_locked

  (bool) –

  The new mutability status for this instance.

• recursive

  (bool, default: False ) –

  Whether to apply the change recursively to its ports. Defaults to False.

evaluate

evaluate() -> None

Evaluates the gate's output signal based on its input signals.

This method is called when the gate's input signals change, and it updates the gate's output signal accordingly.

all_connections

all_connections(
    include_unconnected: bool,
) -> Dict[str, Dict[int, WireSegmentPath]]

Returns a dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port.

Parameters:

• include_unconnected

  (bool) –

  Whether to include unconnected ports in the result.

Returns:

• Dict[str, Dict[int, WireSegmentPath]] –

  A dictionary mapping port names to their corresponding connection paths.

connect

connect(
    port_name: str,
    ws_path: Optional[WireSegmentPath],
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add connections to the specified port of this instance.

This method can establish multiple connections if a range of indices is provided.

Parameters:

• port_name

  (str) –

  The name of the port where the connection(s) should be established.

• ws_path

  (Optional[WireSegmentPath]) –

  The path of the wire segment that will be connected to this port. If None, the associated port (segment) remains unconnected.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

Raises:

• ObjectLockedError –

  If this instance is currently locked, and no connection can be made.

disconnect

disconnect(port_name: str, index: Optional[int] = None) -> None

Remove an existing connection from a specified port of this instance.

This method disconnects the wire segment at the given index within the specified port_name.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be removed.

• index

  (Optional[int], default: None ) –

  The bit index within the port for this disconnection. Defaults to None, which completely disconnects the port.

Raises:

• ObjectLockedError –

  If this instance is locked.

• ObjectNotFoundError –

  If no port exists with the given name.

get_connection

get_connection(
    port_name: str, index: Optional[NonNegativeInt] = None
) -> Union[WireSegmentPath, Dict[int, WireSegmentPath], None]

Retrieve the connection path associated with a specified port and bit index.

If index is provided, this method returns the wire segment path connected to that specific bit within the port. Otherwise, it returns all connections for the given port as a dictionary mapping indices to WireSegmentPaths.

Parameters:

• port_name

  (str) –

  The name of the port for which to retrieve the connection(s).

• index

  (Optional[NonNegativeInt], default: None ) –

  The bit index within the port. Defaults to None.

Returns:

• Union[WireSegmentPath, Dict[int, WireSegmentPath], None] –

  Union[WireSegmentPath, Dict[int, WireSegmentPath]]: Either a single WireSegmentPath or a dictionary mapping indices to WireSegmentPaths.

modify_connection

modify_connection(
    port_name: str, ws_path: WireSegmentPath, index: NonNegativeInt = 0
) -> None

Modify an existing connection within a specified port of this instance.

This method updates the wire segment path at the given index within the specified port_name. If the index does not exist yet, it is newly added, changing the width of the port.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be modified.

• ws_path

  (WireSegmentPath) –

  The new wire segment path for this connection.

• index

  (NonNegativeInt, default: 0 ) –

  The bit index within the port. Defaults to 0.

connect_modify

connect_modify(
    port_name: str,
    ws_path: WireSegmentPath,
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add a new connection or modify an existing one within the specified port of this instance.

If the connection already exists at the given index and port_name, it will be modified. Otherwise, a new connection is added.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be established or updated.

• ws_path

  (WireSegmentPath) –

  The path of the wire segment that will be connected to this port.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

tie_port

tie_port(name: str, index: NonNegativeInt, sig_value: LogicLevel) -> None

Set a constant signal value for the specified port and bit index.

If the specified port does not exist, an error message is logged and the function returns False. Otherwise, the method tries to set the constant signal value for that port and returns True if successful.

Does not work for instance output ports, as they are always driven by their parent instances.

Parameters:

• name

  (str) –

  The name of the port.

• index

  (NonNegativeInt) –

  The bit index within the port.

• sig_value

  (LogicLevel) –

  The constant signal value to be set ('0', '1', or 'Z').

Raises:

• ObjectNotFoundError –

  If no such port or port segment exists.

• AlreadyConnectedError –

  (raised by: PortSegment.tie_signal) If this segment is belongs to a load port and is already connected to a wire, from which it receives its value.

• InvalidDirectionError –

  (raised by: PortSegment.tie_signal) If this port segment belongs to an instance output port, which is driven by the instance inputs and the instance's internal logic.

• InvalidSignalError –

  (raised by: PortSegment.tie_signal) If an invalid value is provided.

has_tied_ports

has_tied_ports() -> bool

Checks the ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any ports of this instance are tied to constant values. False otherwise, i.e. all ports are connected to wires.

has_tied_inputs

has_tied_inputs() -> bool

Checks the input ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any input ports of this instance are tied to constant values. False otherwise, i.e. all input ports are connected to wires.

has_tied_outputs

has_tied_outputs() -> bool

Checks the output ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any output ports of this instance are tied to constant values. False otherwise, i.e. all output ports are connected to wires.

update_signedness

update_signedness(port_name: str) -> None

Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

Parameters:

• port_name

  (str) –

  The name of the port, of which the signedness value is retrieved.

split

split() -> Dict[NonNegativeInt, Self]

Performs a bit-wise split on this instance.

If this instance supports splitting and has a data width of n bit, this method splits this instance into n 1-bit instances. This works for instances, where each output bit depends only on the corresponding input bit(s), e.g. an AND gate or a D-Flipflop.

Returns:

• Dict[NonNegativeInt, Self] –

  Dict[int, Instance]: An n-bit large dictionary, where each key conforms to a bit of the original instance, and each value is an 1-bit instance representing the corresponding "slice" of the original instance.

Raises:

• SplittingUnsupportedError –

  If this instance does not support splitting. Happens for any gate or instance whose behavior depends on the whole bus, and splitting would make it lose its meaning.

p2v

p2v(
    port: ANY_PORT,
    exclude_indices: Optional[List[int]] = None,
    include_indices: Optional[List[int]] = None,
) -> str

Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a Port object and converts them to their corresponding Verilog signal structure (p2v -> Port to Verilog signal syntax). For each segment of the port, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port is set to a constant, the corresponding constant wire segment placeholder is used instead. Port segments can be excluded from the conversion by providing a list of indices to the exclude_indices parameter, indicating which segments should be excluded from the conversion (e.g. segments that are known to be unconnected). Vice versa, only a certain subset of the port's segments may be converted to Verilog syntax, if include_indices is a given list of port indices. All indices not present in the list will be excluded from the conversion.

Parameters:

• port

  (Port) –

  The Port object to convert.

• exclude_indices

  (List[int], default: None ) –

  A list of indices to exclude from the conversion. Defaults to None.

• include_indices

  (List[int], default: None ) –

  A list of indices (i.e. port slices) to include only for the conversion. Defaults to None.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

ps2v

ps2v(ps_dict: Dict[int, PortSegment]) -> str

Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a PortSegment dictionary and converts them to their corresponding Verilog signal structure (ps2v -> PortSegment to Verilog signal syntax). For each segment, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port segment is set to a constant, the corresponding constant wire segment placeholder is used instead.

Parameters:

• ps_dict

  (Dict[int, PortSegment]) –

  The PortSegment dictionary to convert. Each key (int) conforms to the index of the associated PortSegment object.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

• UnsupportedOperationError –

  If two segments belong to different modules.

set

set(
    port_name: str,
    new_signal: SignalOrLogicLevel,
    idx: Union[int, List[int]] = 0,
) -> None

Sets the signal on a port.

Parameters:

• port_name

  (str) –

  The name of the port to set the signal on.

• new_signal

  (Signal) –

  The new signal value.

• idx

  (Union[int, List[int]], default: 0 ) –

  The index (or indices) to apply the given signal to. Can either be an integer (single index to set) or an iterable of integers (e.g. a list of indices). For every integer of the iterable the signal value of the corresponding port index is set to the given new_signal. Defaults to 0.

Example

from netlist_carpentry.utils.gate_factory import and_gate module = Module(name='m') a = module.create_port('a', 'input', width=6) instance = and_gate(module, 'inst', A=a)

This sets the value of bit 0 of port A to HIGH

instance.set('A', 1, 0) instance.ports['A'].signal_str 'xxxxx1'

This sets the value of bits 1, 3 and 5 of port A to LOW, leaving the other bits as they already are.

instance.set('A', 0, [1, 3, 5]) instance.ports['A'].signal_str '0x0x01'

ArithmeticGate

Bases: BinaryGate, BaseModel

A base class for arithmetic gates.

Arithmetic gates are gates that have two input signals representing numeric values, and they produce a single output signal. This class provides a common interface for all arithmetic gates, including methods for evaluating the gate's output and setting its output signal.

Methods:

• change_mutability –

  Change the mutability status of this instance and optionally its ports.

• evaluate –

  Evaluates the gate's output signal based on its input signals.

• all_connections –

  Returns a dictionary mapping port names to their corresponding connection paths.

• model_post_init –

  Initializes the gate's ports and connections.

• connect –

  Add connections to the specified port of this instance.

• disconnect –

  Remove an existing connection from a specified port of this instance.

• get_connection –

  Retrieve the connection path associated with a specified port and bit index.

• modify_connection –

  Modify an existing connection within a specified port of this instance.

• connect_modify –

  Add a new connection or modify an existing one within the specified port of this instance.

• tie_port –

  Set a constant signal value for the specified port and bit index.

• has_tied_ports –

  Checks the ports of this instance whether any are tied to constant values.

• has_tied_inputs –

  Checks the input ports of this instance whether any are tied to constant values.

• has_tied_outputs –

  Checks the output ports of this instance whether any are tied to constant values.

• update_signedness –

  Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

• split –

  Performs a bit-wise split on this instance.

• p2v –

  Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

• ps2v –

  Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

• set –

  Sets the signal on a port.

• get_result –

  Returns the result of this gate's operation for given Signals s1 and s2.

• get_result_vector –

  Returns the result of this gate's operation for full signal vectors.

• signals_in –

  The input signals of the gate.

• signal_out –

  The output signal of the gate.

Attributes:

• input_ports (Tuple[Port[Instance], Port[Instance]]) –

  The input ports of the gate.

• output_port (Port[Instance]) –

  The output port of the gate.

• name (str) –

  The name of the element.

• metadata (MetadataMixin) –

  Metadata of a netlist element.

• path (InstancePath) –

  Returns the InstancePath of the netlist element.

• type (EType) –

  The type of the element, which is an instance.

• hierarchy_level (int) –

  The level of hierarchy of the element in the design.

• has_parent (bool) –

  Whether this object has a parent.

• circuit ('Circuit') –

  The circuit object to which this netlist element belongs to.

• has_circuit (bool) –

  Whether this netlist element has a defined circuit it belongs to.

• locked (bool) –

  True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

• is_placeholder_instance (bool) –

  A placeholder represents an element that does not have a specific path.

• can_carry_signal (bool) –

  Whether this exact object is able to receive, pass or hold signal values.

• instance_type (str) –

  Identifier for instances of this gate type.

• connections (Dict[str, Dict[int, WireSegmentPath]]) –

  A dictionary mapping port names to their corresponding connection paths.

• connection_str_paths (Dict[str, Dict[int, str]]) –

  Returns a dictionary mapping port names to their corresponding connection paths as strings.

• ports (CustomDict[str, Port[Instance]]) –

  A dictionary mapping port names to their corresponding Port objects.

• output_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of output ports associated with this instance.

• has_unconnected_port_segments (bool) –

  Returns True if the instance has at least one unconnected port segment.

• signals (Dict[str, SignalArray]) –

  A dictionary with all signals currently present on all ports of this instance.

• is_blackbox (bool) –

  Flag indicating whether the instance represents neither a primitive element nor a module instance.

• y_width (PositiveInt) –

  Width of the gate, based on a certain port's width, depending on the actual gate.

• a_width (PositiveInt) –

  Width of the gate's A port.

• b_width (PositiveInt) –

  Width of the gate's B port.

• is_combinational (bool) –

  Whether instances of this gate are considered combinational gates.

• is_sequential (bool) –

  Whether instances of this gate are considered sequential gates.

• data_width (int) –

  The data width of this instance.

• a_signed (bool) –

  The signedness of input port A.

• b_signed (bool) –

  The signedness of input port B.

• truth_table (Dict[Tuple[Signal, Signal], Signal]) –

  A simple truth table as a dictionary.

input_ports property

input_ports: Tuple[Port[Instance], Port[Instance]]

The input ports of the gate.

Returns:

• Tuple[Port[Instance], Port[Instance]] –

  Tuple[Port, Port]: The input ports of the gate.

output_port property

output_port: Port[Instance]

The output port of the gate.

Returns:

• Port ( Port[Instance] ) –

  The output port of the gate.

name instance-attribute

name: str

The name of the element.

!!! Do not modify this variable after instantiating it. Use NetlistElement.set_name() instead. Modifying this variable might lead to inconsistencies later on.

metadata class-attribute instance-attribute

metadata: MetadataMixin = MetadataMixin()

Metadata of a netlist element.

Can be user-defined, or e. g. by Yosys (such as src for the HDL source). Is also grouped by categories, i.e. all metadata from Yosys can be accessed via Module.metadata["yosys"], or via Module.metadata.yosys, which both return a dictionary of all metadata. Read the documentation of MetaDataMixin for more information.

path property

path: InstancePath

Returns the InstancePath of the netlist element.

The InstancePath object is constructed using the element's type and its raw hierarchical path.

Returns:

• InstancePath ( InstancePath ) –

  The hierarchical path of the netlist element.

type property

type: EType

The type of the element, which is an instance.

hierarchy_level property

hierarchy_level: int

The level of hierarchy of the element in the design.

The hierarchy level is the number of separators in the element's raw path. For example, a top-level instance has a hierarchy level of 0, while a direct submodule instance has a hierarchy level of 1.

Returns:

• int ( int ) –

  The hierarchy level of the element.

has_parent property

has_parent: bool

Whether this object has a parent.

circuit property

circuit: 'Circuit'

The circuit object to which this netlist element belongs to.

• For a module, returns the circuit to which the module belongs.
• For any other netlist element, recursively returns the circuit of the parent, which ultimately leads to a module, to which the netlist element belongs.

Raises:

• ParentNotFoundError –

  If a parent cannot be resolved somewhere in the hierarchical chain.

• ObjectNotFoundError –

  If for a module no circuit is set.

has_circuit property

has_circuit: bool

Whether this netlist element has a defined circuit it belongs to.

Tries to access self.circuit and returns whether the call was successful. Can be used instead of a try-except clause around the call to NetlistElement.circuit.

locked property

locked: bool

True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

Can be changed via NetlistElement.change_mutability(bool).

Immutability is used to prevent accidental changes to the design.

is_placeholder_instance property

is_placeholder_instance: bool

A placeholder represents an element that does not have a specific path.

True if this NetlistElement instance represents a placeholder, False otherwise.

can_carry_signal property

can_carry_signal: bool

Whether this exact object is able to receive, pass or hold signal values.

True for ports (as they drive or receive values) and wires (as they pass the signals from driver to load ports) as well as their respective segments. False for instances and modules.

instance_type class-attribute instance-attribute

instance_type: str = CFG.id_internal

Identifier for instances of this gate type.

connections property

connections: Dict[str, Dict[int, WireSegmentPath]]

A dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port. Elements with no connection (i.e. the path is None) are excluded. In case these are needed, use Instance.get_connections() instead.

Example

{ 'port1': {1: WireSegmentPath('path/to/element1'), 2: WireSegmentPath('path/to/element2')}, 'port2': {1: WireSegmentPath('path/to/element3')} }

connection_str_paths property

connection_str_paths: Dict[str, Dict[int, str]]

Returns a dictionary mapping port names to their corresponding connection paths as strings.

The keys are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are the raw string paths.

Example

{ 'port1': {0: 'path.to.element1', 1: 'path.to.element2'}, 'port2': {0: 'path.to.element3'} }

ports property

ports: CustomDict[str, Port[Instance]]

A dictionary mapping port names to their corresponding Port objects.

The keys of the dictionary are the names of the ports. The values are Port objects representing the ports.

Returns:

• CustomDict[str, Port[Instance]] –

  A dictionary mapping port names to their corresponding Port objects.

output_ports property

output_ports: Tuple[Port[Instance], ...]

Returns a tuple of output ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as outputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the output ports.

has_unconnected_port_segments property

has_unconnected_port_segments: bool

Returns True if the instance has at least one unconnected port segment.

signals property

signals: Dict[str, SignalArray]

A dictionary with all signals currently present on all ports of this instance.

is_blackbox property

is_blackbox: bool

Flag indicating whether the instance represents neither a primitive element nor a module instance.

If True, this instance does not have a module definition, and is also not a basic component (i.e. a primitive gate instance) from the internal gate library, such as a gate or flip-flop.

y_width property

y_width: PositiveInt

Width of the gate, based on a certain port's width, depending on the actual gate.

a_width property

a_width: PositiveInt

Width of the gate's A port.

b_width property

b_width: PositiveInt

Width of the gate's B port.

is_combinational property

is_combinational: bool

Whether instances of this gate are considered combinational gates.

True for combinational gates, such as AND gates or arithmetic gates. False for flip-flops and latches.

is_sequential property

is_sequential: bool

Whether instances of this gate are considered sequential gates.

False for combinational gates, such as AND gates or arithmetic gates. True for flip-flops and latches.

data_width property

data_width: int

The data width of this instance.

Defaults to the data width of the output port. Can be overwritten in extended classes.

In contrast to self.width, which is used for the creation and initialization, this property is linked to the data width of the output port. This property is useful when the data width of the output port can be changed.

a_signed property

a_signed: bool

The signedness of input port A.

b_signed property

b_signed: bool

The signedness of input port B.

truth_table property

truth_table: Dict[Tuple[Signal, Signal], Signal]

A simple truth table as a dictionary.

This dictionary contains the input-output mapping for unary gates that evaluate bitwise (e.g. AndGate, OrGate). Not implemented for arithmetic gates (e.g. Adder).

change_mutability

change_mutability(is_now_locked: bool, recursive: bool = False) -> Self

Change the mutability status of this instance and optionally its ports.

This method allows setting whether this instance can be modified or not. If recursive is set to True, it also applies the same mutability status to all ports of this instance.

Parameters:

• is_now_locked

  (bool) –

  The new mutability status for this instance.

• recursive

  (bool, default: False ) –

  Whether to apply the change recursively to its ports. Defaults to False.

evaluate

evaluate() -> None

Evaluates the gate's output signal based on its input signals.

This method is called when the gate's input signals change, and it updates the gate's output signal accordingly.

all_connections

all_connections(
    include_unconnected: bool,
) -> Dict[str, Dict[int, WireSegmentPath]]

Returns a dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port.

Parameters:

• include_unconnected

  (bool) –

  Whether to include unconnected ports in the result.

Returns:

• Dict[str, Dict[int, WireSegmentPath]] –

  A dictionary mapping port names to their corresponding connection paths.

model_post_init

model_post_init(__context: object) -> None

Initializes the gate's ports and connections.

This method is called after the gate's attributes have been initialized, and it sets up the gate's ports and connections.

connect

connect(
    port_name: str,
    ws_path: Optional[WireSegmentPath],
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add connections to the specified port of this instance.

This method can establish multiple connections if a range of indices is provided.

Parameters:

• port_name

  (str) –

  The name of the port where the connection(s) should be established.

• ws_path

  (Optional[WireSegmentPath]) –

  The path of the wire segment that will be connected to this port. If None, the associated port (segment) remains unconnected.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

Raises:

• ObjectLockedError –

  If this instance is currently locked, and no connection can be made.

disconnect

disconnect(port_name: str, index: Optional[int] = None) -> None

Remove an existing connection from a specified port of this instance.

This method disconnects the wire segment at the given index within the specified port_name.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be removed.

• index

  (Optional[int], default: None ) –

  The bit index within the port for this disconnection. Defaults to None, which completely disconnects the port.

Raises:

• ObjectLockedError –

  If this instance is locked.

• ObjectNotFoundError –

  If no port exists with the given name.

get_connection

get_connection(
    port_name: str, index: Optional[NonNegativeInt] = None
) -> Union[WireSegmentPath, Dict[int, WireSegmentPath], None]

Retrieve the connection path associated with a specified port and bit index.

If index is provided, this method returns the wire segment path connected to that specific bit within the port. Otherwise, it returns all connections for the given port as a dictionary mapping indices to WireSegmentPaths.

Parameters:

• port_name

  (str) –

  The name of the port for which to retrieve the connection(s).

• index

  (Optional[NonNegativeInt], default: None ) –

  The bit index within the port. Defaults to None.

Returns:

• Union[WireSegmentPath, Dict[int, WireSegmentPath], None] –

  Union[WireSegmentPath, Dict[int, WireSegmentPath]]: Either a single WireSegmentPath or a dictionary mapping indices to WireSegmentPaths.

modify_connection

modify_connection(
    port_name: str, ws_path: WireSegmentPath, index: NonNegativeInt = 0
) -> None

Modify an existing connection within a specified port of this instance.

This method updates the wire segment path at the given index within the specified port_name. If the index does not exist yet, it is newly added, changing the width of the port.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be modified.

• ws_path

  (WireSegmentPath) –

  The new wire segment path for this connection.

• index

  (NonNegativeInt, default: 0 ) –

  The bit index within the port. Defaults to 0.

connect_modify

connect_modify(
    port_name: str,
    ws_path: WireSegmentPath,
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add a new connection or modify an existing one within the specified port of this instance.

If the connection already exists at the given index and port_name, it will be modified. Otherwise, a new connection is added.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be established or updated.

• ws_path

  (WireSegmentPath) –

  The path of the wire segment that will be connected to this port.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

tie_port

tie_port(name: str, index: NonNegativeInt, sig_value: LogicLevel) -> None

Set a constant signal value for the specified port and bit index.

If the specified port does not exist, an error message is logged and the function returns False. Otherwise, the method tries to set the constant signal value for that port and returns True if successful.

Does not work for instance output ports, as they are always driven by their parent instances.

Parameters:

• name

  (str) –

  The name of the port.

• index

  (NonNegativeInt) –

  The bit index within the port.

• sig_value

  (LogicLevel) –

  The constant signal value to be set ('0', '1', or 'Z').

Raises:

• ObjectNotFoundError –

  If no such port or port segment exists.

• AlreadyConnectedError –

  (raised by: PortSegment.tie_signal) If this segment is belongs to a load port and is already connected to a wire, from which it receives its value.

• InvalidDirectionError –

  (raised by: PortSegment.tie_signal) If this port segment belongs to an instance output port, which is driven by the instance inputs and the instance's internal logic.

• InvalidSignalError –

  (raised by: PortSegment.tie_signal) If an invalid value is provided.

has_tied_ports

has_tied_ports() -> bool

Checks the ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any ports of this instance are tied to constant values. False otherwise, i.e. all ports are connected to wires.

has_tied_inputs

has_tied_inputs() -> bool

Checks the input ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any input ports of this instance are tied to constant values. False otherwise, i.e. all input ports are connected to wires.

has_tied_outputs

has_tied_outputs() -> bool

Checks the output ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any output ports of this instance are tied to constant values. False otherwise, i.e. all output ports are connected to wires.

update_signedness

update_signedness(port_name: str) -> None

Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

Parameters:

• port_name

  (str) –

  The name of the port, of which the signedness value is retrieved.

split

split() -> Dict[NonNegativeInt, Self]

Performs a bit-wise split on this instance.

If this instance supports splitting and has a data width of n bit, this method splits this instance into n 1-bit instances. This works for instances, where each output bit depends only on the corresponding input bit(s), e.g. an AND gate or a D-Flipflop.

Returns:

• Dict[NonNegativeInt, Self] –

  Dict[int, Instance]: An n-bit large dictionary, where each key conforms to a bit of the original instance, and each value is an 1-bit instance representing the corresponding "slice" of the original instance.

Raises:

• SplittingUnsupportedError –

  If this instance does not support splitting. Happens for any gate or instance whose behavior depends on the whole bus, and splitting would make it lose its meaning.

p2v

p2v(
    port: ANY_PORT,
    exclude_indices: Optional[List[int]] = None,
    include_indices: Optional[List[int]] = None,
) -> str

Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a Port object and converts them to their corresponding Verilog signal structure (p2v -> Port to Verilog signal syntax). For each segment of the port, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port is set to a constant, the corresponding constant wire segment placeholder is used instead. Port segments can be excluded from the conversion by providing a list of indices to the exclude_indices parameter, indicating which segments should be excluded from the conversion (e.g. segments that are known to be unconnected). Vice versa, only a certain subset of the port's segments may be converted to Verilog syntax, if include_indices is a given list of port indices. All indices not present in the list will be excluded from the conversion.

Parameters:

• port

  (Port) –

  The Port object to convert.

• exclude_indices

  (List[int], default: None ) –

  A list of indices to exclude from the conversion. Defaults to None.

• include_indices

  (List[int], default: None ) –

  A list of indices (i.e. port slices) to include only for the conversion. Defaults to None.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

ps2v

ps2v(ps_dict: Dict[int, PortSegment]) -> str

Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a PortSegment dictionary and converts them to their corresponding Verilog signal structure (ps2v -> PortSegment to Verilog signal syntax). For each segment, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port segment is set to a constant, the corresponding constant wire segment placeholder is used instead.

Parameters:

• ps_dict

  (Dict[int, PortSegment]) –

  The PortSegment dictionary to convert. Each key (int) conforms to the index of the associated PortSegment object.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

• UnsupportedOperationError –

  If two segments belong to different modules.

set

set(
    port_name: str,
    new_signal: SignalOrLogicLevel,
    idx: Union[int, List[int]] = 0,
) -> None

Sets the signal on a port.

Parameters:

• port_name

  (str) –

  The name of the port to set the signal on.

• new_signal

  (Signal) –

  The new signal value.

• idx

  (Union[int, List[int]], default: 0 ) –

  The index (or indices) to apply the given signal to. Can either be an integer (single index to set) or an iterable of integers (e.g. a list of indices). For every integer of the iterable the signal value of the corresponding port index is set to the given new_signal. Defaults to 0.

Example

from netlist_carpentry.utils.gate_factory import and_gate module = Module(name='m') a = module.create_port('a', 'input', width=6) instance = and_gate(module, 'inst', A=a)

This sets the value of bit 0 of port A to HIGH

instance.set('A', 1, 0) instance.ports['A'].signal_str 'xxxxx1'

This sets the value of bits 1, 3 and 5 of port A to LOW, leaving the other bits as they already are.

instance.set('A', 0, [1, 3, 5]) instance.ports['A'].signal_str '0x0x01'

get_result

get_result(s1: Signal, s2: Signal) -> Signal

Returns the result of this gate's operation for given Signals s1 and s2.

This method is only implemented for bitwise evaluating gates (e.g. AndGate, OrGate). This method raises an UnsupportedOperationError if used on other gates (e.g. Adder).

For vector-level operations on full signal arrays, use :meth:get_result_vector instead.

Parameters:

• s1

  (Signal) –

  The first Signal, i.e. the first operand.

• s2

  (Signal) –

  The second Signal, i.e. the second operand.

Raises:

• UnsupportedOperationError –

  For gates that do not evaluate bitwise (e.g. arithmetic gates).

Returns:

• Signal ( Signal ) –

  The result of this gate's operation on the given signals.

get_result_vector

get_result_vector(s1: SignalArray, s2: SignalArray) -> SignalArray

Returns the result of this gate's operation for full signal vectors.

This method provides a unified interface for all binary gates to operate on :class:SignalArray (multi-bit) inputs. The default implementation iterates over each bit index and calls :meth:get_result for bitwise gates (e.g. AndGate, OrGate, XorGate). Gates that operate on the full vectors (e.g. arithmetic gates like Adder, Subtractor, or comparison gates like LessThan) override this method with their vector-level logic.

For comparison gates that produce a single bit from two N-bit inputs (e.g. LessThan, Equal), the output is a 1-bit :class:SignalArray.

Parameters:

• s1

  (SignalArray) –

  The first input signal array.

• s2

  (SignalArray) –

  The second input signal array.

Returns:

• SignalArray ( SignalArray ) –

  The result of this gate's operation on the given signals. For bitwise gates, this has the same width as the inputs. For comparison/reduction gates, this is a 1-bit SignalArray.

signals_in

signals_in(idx: NonNegativeInt = 0) -> Tuple[Signal, Signal]

The input signals of the gate.

Returns:

• Tuple[Signal, Signal] –

  Tuple[Signal, Signal]: The input signals of the gate.

signal_out

signal_out(idx: NonNegativeInt = 0) -> Signal

The output signal of the gate.

Returns:

• Signal ( Signal ) –

  The output signal of the gate.

BinaryNto1Gate

Bases: _Out1BitMixin, BinaryGate, BaseModel

Methods:

• model_post_init –

  Initializes the gate's ports and connections.

• get_result_vector –

  Returns the result of this N-to-1 gate's operation for full signal vectors.

• change_mutability –

  Change the mutability status of this instance and optionally its ports.

• evaluate –

  Evaluates the gate's output signal based on its input signals.

• all_connections –

  Returns a dictionary mapping port names to their corresponding connection paths.

• connect –

  Add connections to the specified port of this instance.

• disconnect –

  Remove an existing connection from a specified port of this instance.

• get_connection –

  Retrieve the connection path associated with a specified port and bit index.

• modify_connection –

  Modify an existing connection within a specified port of this instance.

• connect_modify –

  Add a new connection or modify an existing one within the specified port of this instance.

• tie_port –

  Set a constant signal value for the specified port and bit index.

• has_tied_ports –

  Checks the ports of this instance whether any are tied to constant values.

• has_tied_inputs –

  Checks the input ports of this instance whether any are tied to constant values.

• has_tied_outputs –

  Checks the output ports of this instance whether any are tied to constant values.

• update_signedness –

  Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

• split –

  Performs a bit-wise split on this instance.

• p2v –

  Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

• ps2v –

  Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

• set –

  Sets the signal on a port.

• get_result –

  Returns the result of this gate's operation for given Signals s1 and s2.

• signals_in –

  The input signals of the gate.

• signal_out –

  The output signal of the gate.

Attributes:

• name (str) –

  The name of the element.

• metadata (MetadataMixin) –

  Metadata of a netlist element.

• path (InstancePath) –

  Returns the InstancePath of the netlist element.

• type (EType) –

  The type of the element, which is an instance.

• hierarchy_level (int) –

  The level of hierarchy of the element in the design.

• has_parent (bool) –

  Whether this object has a parent.

• circuit ('Circuit') –

  The circuit object to which this netlist element belongs to.

• has_circuit (bool) –

  Whether this netlist element has a defined circuit it belongs to.

• locked (bool) –

  True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

• is_placeholder_instance (bool) –

  A placeholder represents an element that does not have a specific path.

• can_carry_signal (bool) –

  Whether this exact object is able to receive, pass or hold signal values.

• instance_type (str) –

  Identifier for instances of this gate type.

• connections (Dict[str, Dict[int, WireSegmentPath]]) –

  A dictionary mapping port names to their corresponding connection paths.

• connection_str_paths (Dict[str, Dict[int, str]]) –

  Returns a dictionary mapping port names to their corresponding connection paths as strings.

• ports (CustomDict[str, Port[Instance]]) –

  A dictionary mapping port names to their corresponding Port objects.

• input_ports (Tuple[Port[Instance], Port[Instance]]) –

  The input ports of the gate as a 2-tuple.

• output_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of output ports associated with this instance.

• has_unconnected_port_segments (bool) –

  Returns True if the instance has at least one unconnected port segment.

• signals (Dict[str, SignalArray]) –

  A dictionary with all signals currently present on all ports of this instance.

• is_blackbox (bool) –

  Flag indicating whether the instance represents neither a primitive element nor a module instance.

• y_width (PositiveInt) –

  Width of the gate, which is always 1 for gates that reduce N-bit inputs to 1 bit.

• a_width (PositiveInt) –

  Width of the gate's A port.

• b_width (PositiveInt) –

  Width of the gate's B port.

• is_combinational (bool) –

  Whether instances of this gate are considered combinational gates.

• is_sequential (bool) –

  Whether instances of this gate are considered sequential gates.

• output_port (Port[Instance]) –

  The output port of the gate.

• data_width (int) –

  The data width of this instance.

• a_signed (bool) –

  The signedness of input port A.

• b_signed (bool) –

  The signedness of input port B.

• truth_table (Dict[Tuple[Signal, Signal], Signal]) –

  A simple truth table as a dictionary.

name instance-attribute

name: str

The name of the element.

!!! Do not modify this variable after instantiating it. Use NetlistElement.set_name() instead. Modifying this variable might lead to inconsistencies later on.

metadata class-attribute instance-attribute

metadata: MetadataMixin = MetadataMixin()

Metadata of a netlist element.

Can be user-defined, or e. g. by Yosys (such as src for the HDL source). Is also grouped by categories, i.e. all metadata from Yosys can be accessed via Module.metadata["yosys"], or via Module.metadata.yosys, which both return a dictionary of all metadata. Read the documentation of MetaDataMixin for more information.

path property

path: InstancePath

Returns the InstancePath of the netlist element.

The InstancePath object is constructed using the element's type and its raw hierarchical path.

Returns:

• InstancePath ( InstancePath ) –

  The hierarchical path of the netlist element.

type property

type: EType

The type of the element, which is an instance.

hierarchy_level property

hierarchy_level: int

The level of hierarchy of the element in the design.

The hierarchy level is the number of separators in the element's raw path. For example, a top-level instance has a hierarchy level of 0, while a direct submodule instance has a hierarchy level of 1.

Returns:

• int ( int ) –

  The hierarchy level of the element.

has_parent property

has_parent: bool

Whether this object has a parent.

circuit property

circuit: 'Circuit'

The circuit object to which this netlist element belongs to.

• For a module, returns the circuit to which the module belongs.
• For any other netlist element, recursively returns the circuit of the parent, which ultimately leads to a module, to which the netlist element belongs.

Raises:

• ParentNotFoundError –

  If a parent cannot be resolved somewhere in the hierarchical chain.

• ObjectNotFoundError –

  If for a module no circuit is set.

has_circuit property

has_circuit: bool

Whether this netlist element has a defined circuit it belongs to.

Tries to access self.circuit and returns whether the call was successful. Can be used instead of a try-except clause around the call to NetlistElement.circuit.

locked property

locked: bool

True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

Can be changed via NetlistElement.change_mutability(bool).

Immutability is used to prevent accidental changes to the design.

is_placeholder_instance property

is_placeholder_instance: bool

A placeholder represents an element that does not have a specific path.

True if this NetlistElement instance represents a placeholder, False otherwise.

can_carry_signal property

can_carry_signal: bool

Whether this exact object is able to receive, pass or hold signal values.

True for ports (as they drive or receive values) and wires (as they pass the signals from driver to load ports) as well as their respective segments. False for instances and modules.

instance_type class-attribute instance-attribute

instance_type: str = CFG.id_internal

Identifier for instances of this gate type.

connections property

connections: Dict[str, Dict[int, WireSegmentPath]]

A dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port. Elements with no connection (i.e. the path is None) are excluded. In case these are needed, use Instance.get_connections() instead.

Example

{ 'port1': {1: WireSegmentPath('path/to/element1'), 2: WireSegmentPath('path/to/element2')}, 'port2': {1: WireSegmentPath('path/to/element3')} }

connection_str_paths property

connection_str_paths: Dict[str, Dict[int, str]]

Returns a dictionary mapping port names to their corresponding connection paths as strings.

The keys are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are the raw string paths.

Example

{ 'port1': {0: 'path.to.element1', 1: 'path.to.element2'}, 'port2': {0: 'path.to.element3'} }

ports property

ports: CustomDict[str, Port[Instance]]

A dictionary mapping port names to their corresponding Port objects.

The keys of the dictionary are the names of the ports. The values are Port objects representing the ports.

Returns:

• CustomDict[str, Port[Instance]] –

  A dictionary mapping port names to their corresponding Port objects.

input_ports property

input_ports: Tuple[Port[Instance], Port[Instance]]

The input ports of the gate as a 2-tuple.

output_ports property

output_ports: Tuple[Port[Instance], ...]

Returns a tuple of output ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as outputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the output ports.

has_unconnected_port_segments property

has_unconnected_port_segments: bool

Returns True if the instance has at least one unconnected port segment.

signals property

signals: Dict[str, SignalArray]

A dictionary with all signals currently present on all ports of this instance.

is_blackbox property

is_blackbox: bool

Flag indicating whether the instance represents neither a primitive element nor a module instance.

If True, this instance does not have a module definition, and is also not a basic component (i.e. a primitive gate instance) from the internal gate library, such as a gate or flip-flop.

y_width property

y_width: PositiveInt

Width of the gate, which is always 1 for gates that reduce N-bit inputs to 1 bit.

a_width property

a_width: PositiveInt

Width of the gate's A port.

b_width property

b_width: PositiveInt

Width of the gate's B port.

is_combinational property

is_combinational: bool

Whether instances of this gate are considered combinational gates.

True for combinational gates, such as AND gates or arithmetic gates. False for flip-flops and latches.

is_sequential property

is_sequential: bool

Whether instances of this gate are considered sequential gates.

False for combinational gates, such as AND gates or arithmetic gates. True for flip-flops and latches.

output_port property

output_port: Port[Instance]

The output port of the gate.

data_width property

data_width: int

The data width of this instance.

Defaults to the data width of the output port. Can be overwritten in extended classes.

In contrast to self.width, which is used for the creation and initialization, this property is linked to the data width of the output port. This property is useful when the data width of the output port can be changed.

a_signed property

a_signed: bool

The signedness of input port A.

b_signed property

b_signed: bool

The signedness of input port B.

truth_table property

truth_table: Dict[Tuple[Signal, Signal], Signal]

A simple truth table as a dictionary.

This dictionary contains the input-output mapping for unary gates that evaluate bitwise (e.g. AndGate, OrGate). Not implemented for arithmetic gates (e.g. Adder).

model_post_init

model_post_init(__context: object) -> None

Initializes the gate's ports and connections.

This method is called after the gate's attributes have been initialized, and it sets up the gate's ports and connections.

get_result_vector

get_result_vector(s1: SignalArray, s2: SignalArray) -> SignalArray

Returns the result of this N-to-1 gate's operation for full signal vectors.

Reduces two N-bit :class:SignalArray inputs to a 1-bit :class:SignalArray. Concrete subclasses (e.g. LessThan, Equal, GreaterThan) override this method with their specific comparison logic.

Parameters:

• s1

  (SignalArray) –

  The first input signal array.

• s2

  (SignalArray) –

  The second input signal array.

Returns:

• SignalArray ( SignalArray ) –

  A 1-bit SignalArray containing the comparison result.

Raises:

• UnsupportedOperationError –

  If the subclass does not implement vector-level logic.

change_mutability

change_mutability(is_now_locked: bool, recursive: bool = False) -> Self

Change the mutability status of this instance and optionally its ports.

This method allows setting whether this instance can be modified or not. If recursive is set to True, it also applies the same mutability status to all ports of this instance.

Parameters:

• is_now_locked

  (bool) –

  The new mutability status for this instance.

• recursive

  (bool, default: False ) –

  Whether to apply the change recursively to its ports. Defaults to False.

evaluate

evaluate() -> None

Evaluates the gate's output signal based on its input signals.

This method is called when the gate's input signals change, and it updates the gate's output signal accordingly.

all_connections

all_connections(
    include_unconnected: bool,
) -> Dict[str, Dict[int, WireSegmentPath]]

Returns a dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port.

Parameters:

• include_unconnected

  (bool) –

  Whether to include unconnected ports in the result.

Returns:

• Dict[str, Dict[int, WireSegmentPath]] –

  A dictionary mapping port names to their corresponding connection paths.

connect

connect(
    port_name: str,
    ws_path: Optional[WireSegmentPath],
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add connections to the specified port of this instance.

This method can establish multiple connections if a range of indices is provided.

Parameters:

• port_name

  (str) –

  The name of the port where the connection(s) should be established.

• ws_path

  (Optional[WireSegmentPath]) –

  The path of the wire segment that will be connected to this port. If None, the associated port (segment) remains unconnected.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

Raises:

• ObjectLockedError –

  If this instance is currently locked, and no connection can be made.

disconnect

disconnect(port_name: str, index: Optional[int] = None) -> None

Remove an existing connection from a specified port of this instance.

This method disconnects the wire segment at the given index within the specified port_name.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be removed.

• index

  (Optional[int], default: None ) –

  The bit index within the port for this disconnection. Defaults to None, which completely disconnects the port.

Raises:

• ObjectLockedError –

  If this instance is locked.

• ObjectNotFoundError –

  If no port exists with the given name.

get_connection

get_connection(
    port_name: str, index: Optional[NonNegativeInt] = None
) -> Union[WireSegmentPath, Dict[int, WireSegmentPath], None]

Retrieve the connection path associated with a specified port and bit index.

If index is provided, this method returns the wire segment path connected to that specific bit within the port. Otherwise, it returns all connections for the given port as a dictionary mapping indices to WireSegmentPaths.

Parameters:

• port_name

  (str) –

  The name of the port for which to retrieve the connection(s).

• index

  (Optional[NonNegativeInt], default: None ) –

  The bit index within the port. Defaults to None.

Returns:

• Union[WireSegmentPath, Dict[int, WireSegmentPath], None] –

  Union[WireSegmentPath, Dict[int, WireSegmentPath]]: Either a single WireSegmentPath or a dictionary mapping indices to WireSegmentPaths.

modify_connection

modify_connection(
    port_name: str, ws_path: WireSegmentPath, index: NonNegativeInt = 0
) -> None

Modify an existing connection within a specified port of this instance.

This method updates the wire segment path at the given index within the specified port_name. If the index does not exist yet, it is newly added, changing the width of the port.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be modified.

• ws_path

  (WireSegmentPath) –

  The new wire segment path for this connection.

• index

  (NonNegativeInt, default: 0 ) –

  The bit index within the port. Defaults to 0.

connect_modify

connect_modify(
    port_name: str,
    ws_path: WireSegmentPath,
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add a new connection or modify an existing one within the specified port of this instance.

If the connection already exists at the given index and port_name, it will be modified. Otherwise, a new connection is added.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be established or updated.

• ws_path

  (WireSegmentPath) –

  The path of the wire segment that will be connected to this port.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

tie_port

tie_port(name: str, index: NonNegativeInt, sig_value: LogicLevel) -> None

Set a constant signal value for the specified port and bit index.

If the specified port does not exist, an error message is logged and the function returns False. Otherwise, the method tries to set the constant signal value for that port and returns True if successful.

Does not work for instance output ports, as they are always driven by their parent instances.

Parameters:

• name

  (str) –

  The name of the port.

• index

  (NonNegativeInt) –

  The bit index within the port.

• sig_value

  (LogicLevel) –

  The constant signal value to be set ('0', '1', or 'Z').

Raises:

• ObjectNotFoundError –

  If no such port or port segment exists.

• AlreadyConnectedError –

  (raised by: PortSegment.tie_signal) If this segment is belongs to a load port and is already connected to a wire, from which it receives its value.

• InvalidDirectionError –

  (raised by: PortSegment.tie_signal) If this port segment belongs to an instance output port, which is driven by the instance inputs and the instance's internal logic.

• InvalidSignalError –

  (raised by: PortSegment.tie_signal) If an invalid value is provided.

has_tied_ports

has_tied_ports() -> bool

Checks the ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any ports of this instance are tied to constant values. False otherwise, i.e. all ports are connected to wires.

has_tied_inputs

has_tied_inputs() -> bool

Checks the input ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any input ports of this instance are tied to constant values. False otherwise, i.e. all input ports are connected to wires.

has_tied_outputs

has_tied_outputs() -> bool

Checks the output ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any output ports of this instance are tied to constant values. False otherwise, i.e. all output ports are connected to wires.

update_signedness

update_signedness(port_name: str) -> None

Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

Parameters:

• port_name

  (str) –

  The name of the port, of which the signedness value is retrieved.

split

split() -> Dict[NonNegativeInt, Self]

Performs a bit-wise split on this instance.

If this instance supports splitting and has a data width of n bit, this method splits this instance into n 1-bit instances. This works for instances, where each output bit depends only on the corresponding input bit(s), e.g. an AND gate or a D-Flipflop.

Returns:

• Dict[NonNegativeInt, Self] –

  Dict[int, Instance]: An n-bit large dictionary, where each key conforms to a bit of the original instance, and each value is an 1-bit instance representing the corresponding "slice" of the original instance.

Raises:

• SplittingUnsupportedError –

  If this instance does not support splitting. Happens for any gate or instance whose behavior depends on the whole bus, and splitting would make it lose its meaning.

p2v

p2v(
    port: ANY_PORT,
    exclude_indices: Optional[List[int]] = None,
    include_indices: Optional[List[int]] = None,
) -> str

Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a Port object and converts them to their corresponding Verilog signal structure (p2v -> Port to Verilog signal syntax). For each segment of the port, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port is set to a constant, the corresponding constant wire segment placeholder is used instead. Port segments can be excluded from the conversion by providing a list of indices to the exclude_indices parameter, indicating which segments should be excluded from the conversion (e.g. segments that are known to be unconnected). Vice versa, only a certain subset of the port's segments may be converted to Verilog syntax, if include_indices is a given list of port indices. All indices not present in the list will be excluded from the conversion.

Parameters:

• port

  (Port) –

  The Port object to convert.

• exclude_indices

  (List[int], default: None ) –

  A list of indices to exclude from the conversion. Defaults to None.

• include_indices

  (List[int], default: None ) –

  A list of indices (i.e. port slices) to include only for the conversion. Defaults to None.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

ps2v

ps2v(ps_dict: Dict[int, PortSegment]) -> str

Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a PortSegment dictionary and converts them to their corresponding Verilog signal structure (ps2v -> PortSegment to Verilog signal syntax). For each segment, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port segment is set to a constant, the corresponding constant wire segment placeholder is used instead.

Parameters:

• ps_dict

  (Dict[int, PortSegment]) –

  The PortSegment dictionary to convert. Each key (int) conforms to the index of the associated PortSegment object.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

• UnsupportedOperationError –

  If two segments belong to different modules.

set

set(
    port_name: str,
    new_signal: SignalOrLogicLevel,
    idx: Union[int, List[int]] = 0,
) -> None

Sets the signal on a port.

Parameters:

• port_name

  (str) –

  The name of the port to set the signal on.

• new_signal

  (Signal) –

  The new signal value.

• idx

  (Union[int, List[int]], default: 0 ) –

  The index (or indices) to apply the given signal to. Can either be an integer (single index to set) or an iterable of integers (e.g. a list of indices). For every integer of the iterable the signal value of the corresponding port index is set to the given new_signal. Defaults to 0.

Example

from netlist_carpentry.utils.gate_factory import and_gate module = Module(name='m') a = module.create_port('a', 'input', width=6) instance = and_gate(module, 'inst', A=a)

This sets the value of bit 0 of port A to HIGH

instance.set('A', 1, 0) instance.ports['A'].signal_str 'xxxxx1'

This sets the value of bits 1, 3 and 5 of port A to LOW, leaving the other bits as they already are.

instance.set('A', 0, [1, 3, 5]) instance.ports['A'].signal_str '0x0x01'

get_result

get_result(s1: Signal, s2: Signal) -> Signal

Returns the result of this gate's operation for given Signals s1 and s2.

This method is only implemented for bitwise evaluating gates (e.g. AndGate, OrGate). This method raises an UnsupportedOperationError if used on other gates (e.g. Adder).

For vector-level operations on full signal arrays, use :meth:get_result_vector instead.

Parameters:

• s1

  (Signal) –

  The first Signal, i.e. the first operand.

• s2

  (Signal) –

  The second Signal, i.e. the second operand.

Raises:

• UnsupportedOperationError –

  For gates that do not evaluate bitwise (e.g. arithmetic gates).

Returns:

• Signal ( Signal ) –

  The result of this gate's operation on the given signals.

signals_in

signals_in(idx: NonNegativeInt = 0) -> Tuple[Signal, Signal]

The input signals of the gate.

Returns:

• Tuple[Signal, Signal] –

  Tuple[Signal, Signal]: The input signals of the gate.

signal_out

signal_out(idx: NonNegativeInt = 0) -> Signal

The output signal of the gate.

Returns:

• Signal ( Signal ) –

  The output signal of the gate.

NtoOneGate

Bases: PrimitiveGate, BaseModel

Base class for gates with N data inputs and 1 output (e.g., multiplexers).

Provides common infrastructure for dynamic port creation (D0..Dn), select signal handling, and Verilog case-statement generation. Subclasses only need to implement get_result_vector() for signal evaluation.

Methods:

• get_result_vector –

  Calculate output from select value and data inputs. Subclasses must implement.

• change_mutability –

  Change the mutability status of this instance and optionally its ports.

• evaluate –

  Evaluates the gate's output signal based on its input signals.

• all_connections –

  Returns a dictionary mapping port names to their corresponding connection paths.

• connect –

  Add connections to the specified port of this instance.

• disconnect –

  Remove an existing connection from a specified port of this instance.

• get_connection –

  Retrieve the connection path associated with a specified port and bit index.

• modify_connection –

  Modify an existing connection within a specified port of this instance.

• connect_modify –

  Add a new connection or modify an existing one within the specified port of this instance.

• tie_port –

  Set a constant signal value for the specified port and bit index.

• has_tied_ports –

  Checks the ports of this instance whether any are tied to constant values.

• has_tied_inputs –

  Checks the input ports of this instance whether any are tied to constant values.

• has_tied_outputs –

  Checks the output ports of this instance whether any are tied to constant values.

• update_signedness –

  Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

• split –

  Performs a bit-wise split on this instance.

• p2v –

  Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

• ps2v –

  Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

• set –

  Sets the signal on a port.

Attributes:

• bit_width (int) –

  Width of the select/control signal.

• y_width (PositiveInt) –

  Width of the output/data port.

• s_defined (bool) –

  Whether all select signal bits are defined.

• s_val (int) –

  Integer value of the select signals, or -1 if undefined.

• s_port (Port[Instance]) –

  The select/control port.

• active_input (Optional[Port[Instance]]) –

  The active input port based on select value.

• name (str) –

  The name of the element.

• metadata (MetadataMixin) –

  Metadata of a netlist element.

• path (InstancePath) –

  Returns the InstancePath of the netlist element.

• type (EType) –

  The type of the element, which is an instance.

• hierarchy_level (int) –

  The level of hierarchy of the element in the design.

• has_parent (bool) –

  Whether this object has a parent.

• circuit ('Circuit') –

  The circuit object to which this netlist element belongs to.

• has_circuit (bool) –

  Whether this netlist element has a defined circuit it belongs to.

• locked (bool) –

  True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

• is_placeholder_instance (bool) –

  A placeholder represents an element that does not have a specific path.

• can_carry_signal (bool) –

  Whether this exact object is able to receive, pass or hold signal values.

• instance_type (str) –

  Identifier for instances of this gate type.

• connections (Dict[str, Dict[int, WireSegmentPath]]) –

  A dictionary mapping port names to their corresponding connection paths.

• connection_str_paths (Dict[str, Dict[int, str]]) –

  Returns a dictionary mapping port names to their corresponding connection paths as strings.

• ports (CustomDict[str, Port[Instance]]) –

  A dictionary mapping port names to their corresponding Port objects.

• input_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of input ports associated with this instance.

• output_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of output ports associated with this instance.

• has_unconnected_port_segments (bool) –

  Returns True if the instance has at least one unconnected port segment.

• signals (Dict[str, SignalArray]) –

  A dictionary with all signals currently present on all ports of this instance.

• is_blackbox (bool) –

  Flag indicating whether the instance represents neither a primitive element nor a module instance.

• a_width (PositiveInt) –

  Width of the gate's A port.

• b_width (PositiveInt) –

  Width of the gate's B port.

• is_combinational (bool) –

  Whether instances of this gate are considered combinational gates.

• is_sequential (bool) –

  Whether instances of this gate are considered sequential gates.

• data_width (int) –

  The data width of this instance.

bit_width property writable

bit_width: int

Width of the select/control signal.

y_width property writable

y_width: PositiveInt

Width of the output/data port.

s_defined property

s_defined: bool

Whether all select signal bits are defined.

s_val property

s_val: int

Integer value of the select signals, or -1 if undefined.

s_port property

s_port: Port[Instance]

The select/control port.

active_input property

active_input: Optional[Port[Instance]]

The active input port based on select value.

name instance-attribute

name: str

The name of the element.

!!! Do not modify this variable after instantiating it. Use NetlistElement.set_name() instead. Modifying this variable might lead to inconsistencies later on.

metadata class-attribute instance-attribute

metadata: MetadataMixin = MetadataMixin()

Metadata of a netlist element.

Can be user-defined, or e. g. by Yosys (such as src for the HDL source). Is also grouped by categories, i.e. all metadata from Yosys can be accessed via Module.metadata["yosys"], or via Module.metadata.yosys, which both return a dictionary of all metadata. Read the documentation of MetaDataMixin for more information.

path property

path: InstancePath

Returns the InstancePath of the netlist element.

The InstancePath object is constructed using the element's type and its raw hierarchical path.

Returns:

• InstancePath ( InstancePath ) –

  The hierarchical path of the netlist element.

type property

type: EType

The type of the element, which is an instance.

hierarchy_level property

hierarchy_level: int

The level of hierarchy of the element in the design.

The hierarchy level is the number of separators in the element's raw path. For example, a top-level instance has a hierarchy level of 0, while a direct submodule instance has a hierarchy level of 1.

Returns:

• int ( int ) –

  The hierarchy level of the element.

has_parent property

has_parent: bool

Whether this object has a parent.

circuit property

circuit: 'Circuit'

The circuit object to which this netlist element belongs to.

• For a module, returns the circuit to which the module belongs.
• For any other netlist element, recursively returns the circuit of the parent, which ultimately leads to a module, to which the netlist element belongs.

Raises:

• ParentNotFoundError –

  If a parent cannot be resolved somewhere in the hierarchical chain.

• ObjectNotFoundError –

  If for a module no circuit is set.

has_circuit property

has_circuit: bool

Whether this netlist element has a defined circuit it belongs to.

Tries to access self.circuit and returns whether the call was successful. Can be used instead of a try-except clause around the call to NetlistElement.circuit.

locked property

locked: bool

True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

Can be changed via NetlistElement.change_mutability(bool).

Immutability is used to prevent accidental changes to the design.

is_placeholder_instance property

is_placeholder_instance: bool

A placeholder represents an element that does not have a specific path.

True if this NetlistElement instance represents a placeholder, False otherwise.

can_carry_signal property

can_carry_signal: bool

Whether this exact object is able to receive, pass or hold signal values.

True for ports (as they drive or receive values) and wires (as they pass the signals from driver to load ports) as well as their respective segments. False for instances and modules.

instance_type class-attribute instance-attribute

instance_type: str = CFG.id_internal

Identifier for instances of this gate type.

connections property

connections: Dict[str, Dict[int, WireSegmentPath]]

A dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port. Elements with no connection (i.e. the path is None) are excluded. In case these are needed, use Instance.get_connections() instead.

Example

{ 'port1': {1: WireSegmentPath('path/to/element1'), 2: WireSegmentPath('path/to/element2')}, 'port2': {1: WireSegmentPath('path/to/element3')} }

connection_str_paths property

connection_str_paths: Dict[str, Dict[int, str]]

Returns a dictionary mapping port names to their corresponding connection paths as strings.

The keys are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are the raw string paths.

Example

{ 'port1': {0: 'path.to.element1', 1: 'path.to.element2'}, 'port2': {0: 'path.to.element3'} }

ports property

ports: CustomDict[str, Port[Instance]]

A dictionary mapping port names to their corresponding Port objects.

The keys of the dictionary are the names of the ports. The values are Port objects representing the ports.

Returns:

• CustomDict[str, Port[Instance]] –

  A dictionary mapping port names to their corresponding Port objects.

input_ports property

input_ports: Tuple[Port[Instance], ...]

Returns a tuple of input ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as inputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the input ports.

output_ports property

output_ports: Tuple[Port[Instance], ...]

Returns a tuple of output ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as outputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the output ports.

has_unconnected_port_segments property

has_unconnected_port_segments: bool

Returns True if the instance has at least one unconnected port segment.

signals property

signals: Dict[str, SignalArray]

A dictionary with all signals currently present on all ports of this instance.

is_blackbox property

is_blackbox: bool

Flag indicating whether the instance represents neither a primitive element nor a module instance.

If True, this instance does not have a module definition, and is also not a basic component (i.e. a primitive gate instance) from the internal gate library, such as a gate or flip-flop.

a_width property

a_width: PositiveInt

Width of the gate's A port.

b_width property

b_width: PositiveInt

Width of the gate's B port.

is_combinational property

is_combinational: bool

Whether instances of this gate are considered combinational gates.

True for combinational gates, such as AND gates or arithmetic gates. False for flip-flops and latches.

is_sequential property

is_sequential: bool

Whether instances of this gate are considered sequential gates.

False for combinational gates, such as AND gates or arithmetic gates. True for flip-flops and latches.

data_width property

data_width: int

The data width of this instance.

Defaults to the data width of the output port. Can be overwritten in extended classes.

In contrast to self.width, which is used for the creation and initialization, this property is linked to the data width of the output port. This property is useful when the data width of the output port can be changed.

get_result_vector

get_result_vector(
    select: SignalArray, data: Dict[str, SignalArray]
) -> SignalArray

Calculate output from select value and data inputs. Subclasses must implement.

change_mutability

change_mutability(is_now_locked: bool, recursive: bool = False) -> Self

Change the mutability status of this instance and optionally its ports.

This method allows setting whether this instance can be modified or not. If recursive is set to True, it also applies the same mutability status to all ports of this instance.

Parameters:

• is_now_locked

  (bool) –

  The new mutability status for this instance.

• recursive

  (bool, default: False ) –

  Whether to apply the change recursively to its ports. Defaults to False.

evaluate

evaluate() -> None

Evaluates the gate's output signal based on its input signals.

This method is called when the gate's input signals change, and it updates the gate's output signal accordingly.

all_connections

all_connections(
    include_unconnected: bool,
) -> Dict[str, Dict[int, WireSegmentPath]]

Returns a dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port.

Parameters:

• include_unconnected

  (bool) –

  Whether to include unconnected ports in the result.

Returns:

• Dict[str, Dict[int, WireSegmentPath]] –

  A dictionary mapping port names to their corresponding connection paths.

connect

connect(
    port_name: str,
    ws_path: Optional[WireSegmentPath],
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add connections to the specified port of this instance.

This method can establish multiple connections if a range of indices is provided.

Parameters:

• port_name

  (str) –

  The name of the port where the connection(s) should be established.

• ws_path

  (Optional[WireSegmentPath]) –

  The path of the wire segment that will be connected to this port. If None, the associated port (segment) remains unconnected.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

Raises:

• ObjectLockedError –

  If this instance is currently locked, and no connection can be made.

disconnect

disconnect(port_name: str, index: Optional[int] = None) -> None

Remove an existing connection from a specified port of this instance.

This method disconnects the wire segment at the given index within the specified port_name.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be removed.

• index

  (Optional[int], default: None ) –

  The bit index within the port for this disconnection. Defaults to None, which completely disconnects the port.

Raises:

• ObjectLockedError –

  If this instance is locked.

• ObjectNotFoundError –

  If no port exists with the given name.

get_connection

get_connection(
    port_name: str, index: Optional[NonNegativeInt] = None
) -> Union[WireSegmentPath, Dict[int, WireSegmentPath], None]

Retrieve the connection path associated with a specified port and bit index.

If index is provided, this method returns the wire segment path connected to that specific bit within the port. Otherwise, it returns all connections for the given port as a dictionary mapping indices to WireSegmentPaths.

Parameters:

• port_name

  (str) –

  The name of the port for which to retrieve the connection(s).

• index

  (Optional[NonNegativeInt], default: None ) –

  The bit index within the port. Defaults to None.

Returns:

• Union[WireSegmentPath, Dict[int, WireSegmentPath], None] –

  Union[WireSegmentPath, Dict[int, WireSegmentPath]]: Either a single WireSegmentPath or a dictionary mapping indices to WireSegmentPaths.

modify_connection

modify_connection(
    port_name: str, ws_path: WireSegmentPath, index: NonNegativeInt = 0
) -> None

Modify an existing connection within a specified port of this instance.

This method updates the wire segment path at the given index within the specified port_name. If the index does not exist yet, it is newly added, changing the width of the port.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be modified.

• ws_path

  (WireSegmentPath) –

  The new wire segment path for this connection.

• index

  (NonNegativeInt, default: 0 ) –

  The bit index within the port. Defaults to 0.

connect_modify

connect_modify(
    port_name: str,
    ws_path: WireSegmentPath,
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add a new connection or modify an existing one within the specified port of this instance.

If the connection already exists at the given index and port_name, it will be modified. Otherwise, a new connection is added.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be established or updated.

• ws_path

  (WireSegmentPath) –

  The path of the wire segment that will be connected to this port.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

tie_port

tie_port(name: str, index: NonNegativeInt, sig_value: LogicLevel) -> None

Set a constant signal value for the specified port and bit index.

If the specified port does not exist, an error message is logged and the function returns False. Otherwise, the method tries to set the constant signal value for that port and returns True if successful.

Does not work for instance output ports, as they are always driven by their parent instances.

Parameters:

• name

  (str) –

  The name of the port.

• index

  (NonNegativeInt) –

  The bit index within the port.

• sig_value

  (LogicLevel) –

  The constant signal value to be set ('0', '1', or 'Z').

Raises:

• ObjectNotFoundError –

  If no such port or port segment exists.

• AlreadyConnectedError –

  (raised by: PortSegment.tie_signal) If this segment is belongs to a load port and is already connected to a wire, from which it receives its value.

• InvalidDirectionError –

  (raised by: PortSegment.tie_signal) If this port segment belongs to an instance output port, which is driven by the instance inputs and the instance's internal logic.

• InvalidSignalError –

  (raised by: PortSegment.tie_signal) If an invalid value is provided.

has_tied_ports

has_tied_ports() -> bool

Checks the ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any ports of this instance are tied to constant values. False otherwise, i.e. all ports are connected to wires.

has_tied_inputs

has_tied_inputs() -> bool

Checks the input ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any input ports of this instance are tied to constant values. False otherwise, i.e. all input ports are connected to wires.

has_tied_outputs

has_tied_outputs() -> bool

Checks the output ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any output ports of this instance are tied to constant values. False otherwise, i.e. all output ports are connected to wires.

update_signedness

update_signedness(port_name: str) -> None

Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

Parameters:

• port_name

  (str) –

  The name of the port, of which the signedness value is retrieved.

split

split() -> Dict[NonNegativeInt, Self]

Performs a bit-wise split on this instance.

If this instance supports splitting and has a data width of n bit, this method splits this instance into n 1-bit instances. This works for instances, where each output bit depends only on the corresponding input bit(s), e.g. an AND gate or a D-Flipflop.

Returns:

• Dict[NonNegativeInt, Self] –

  Dict[int, Instance]: An n-bit large dictionary, where each key conforms to a bit of the original instance, and each value is an 1-bit instance representing the corresponding "slice" of the original instance.

Raises:

• SplittingUnsupportedError –

  If this instance does not support splitting. Happens for any gate or instance whose behavior depends on the whole bus, and splitting would make it lose its meaning.

p2v

p2v(
    port: ANY_PORT,
    exclude_indices: Optional[List[int]] = None,
    include_indices: Optional[List[int]] = None,
) -> str

Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a Port object and converts them to their corresponding Verilog signal structure (p2v -> Port to Verilog signal syntax). For each segment of the port, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port is set to a constant, the corresponding constant wire segment placeholder is used instead. Port segments can be excluded from the conversion by providing a list of indices to the exclude_indices parameter, indicating which segments should be excluded from the conversion (e.g. segments that are known to be unconnected). Vice versa, only a certain subset of the port's segments may be converted to Verilog syntax, if include_indices is a given list of port indices. All indices not present in the list will be excluded from the conversion.

Parameters:

• port

  (Port) –

  The Port object to convert.

• exclude_indices

  (List[int], default: None ) –

  A list of indices to exclude from the conversion. Defaults to None.

• include_indices

  (List[int], default: None ) –

  A list of indices (i.e. port slices) to include only for the conversion. Defaults to None.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

ps2v

ps2v(ps_dict: Dict[int, PortSegment]) -> str

Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a PortSegment dictionary and converts them to their corresponding Verilog signal structure (ps2v -> PortSegment to Verilog signal syntax). For each segment, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port segment is set to a constant, the corresponding constant wire segment placeholder is used instead.

Parameters:

• ps_dict

  (Dict[int, PortSegment]) –

  The PortSegment dictionary to convert. Each key (int) conforms to the index of the associated PortSegment object.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

• UnsupportedOperationError –

  If two segments belong to different modules.

set

set(
    port_name: str,
    new_signal: SignalOrLogicLevel,
    idx: Union[int, List[int]] = 0,
) -> None

Sets the signal on a port.

Parameters:

• port_name

  (str) –

  The name of the port to set the signal on.

• new_signal

  (Signal) –

  The new signal value.

• idx

  (Union[int, List[int]], default: 0 ) –

  The index (or indices) to apply the given signal to. Can either be an integer (single index to set) or an iterable of integers (e.g. a list of indices). For every integer of the iterable the signal value of the corresponding port index is set to the given new_signal. Defaults to 0.

Example

from netlist_carpentry.utils.gate_factory import and_gate module = Module(name='m') a = module.create_port('a', 'input', width=6) instance = and_gate(module, 'inst', A=a)

This sets the value of bit 0 of port A to HIGH

instance.set('A', 1, 0) instance.ports['A'].signal_str 'xxxxx1'

This sets the value of bits 1, 3 and 5 of port A to LOW, leaving the other bits as they already are.

instance.set('A', 0, [1, 3, 5]) instance.ports['A'].signal_str '0x0x01'

OneToNGate

Bases: PrimitiveGate, BaseModel

Base class for gates with 1 input and N data outputs (e.g., demultiplexers).

Provides common infrastructure for dynamic port creation (Y0..Yn), select signal handling, and Verilog case-statement generation. Subclasses only need to implement _set_output() for routing logic.

Methods:

• change_mutability –

  Change the mutability status of this instance and optionally its ports.

• evaluate –

  Evaluates the gate's output signal based on its input signals.

• all_connections –

  Returns a dictionary mapping port names to their corresponding connection paths.

• connect –

  Add connections to the specified port of this instance.

• disconnect –

  Remove an existing connection from a specified port of this instance.

• get_connection –

  Retrieve the connection path associated with a specified port and bit index.

• modify_connection –

  Modify an existing connection within a specified port of this instance.

• connect_modify –

  Add a new connection or modify an existing one within the specified port of this instance.

• tie_port –

  Set a constant signal value for the specified port and bit index.

• has_tied_ports –

  Checks the ports of this instance whether any are tied to constant values.

• has_tied_inputs –

  Checks the input ports of this instance whether any are tied to constant values.

• has_tied_outputs –

  Checks the output ports of this instance whether any are tied to constant values.

• update_signedness –

  Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

• split –

  Performs a bit-wise split on this instance.

• p2v –

  Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

• ps2v –

  Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

• set –

  Sets the signal on a port.

Attributes:

• bit_width (int) –

  Width of the select/control signal.

• y_width (PositiveInt) –

  Width of the input/data port.

• s_defined (bool) –

  Whether all select signal bits are defined.

• s_val (int) –

  Integer value of the select signals, or -1 if undefined.

• active_output (Optional[Port[Instance]]) –

  The active output port based on select value.

• s_port (Port[Instance]) –

  The select/control port.

• name (str) –

  The name of the element.

• metadata (MetadataMixin) –

  Metadata of a netlist element.

• path (InstancePath) –

  Returns the InstancePath of the netlist element.

• type (EType) –

  The type of the element, which is an instance.

• hierarchy_level (int) –

  The level of hierarchy of the element in the design.

• has_parent (bool) –

  Whether this object has a parent.

• circuit ('Circuit') –

  The circuit object to which this netlist element belongs to.

• has_circuit (bool) –

  Whether this netlist element has a defined circuit it belongs to.

• locked (bool) –

  True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

• is_placeholder_instance (bool) –

  A placeholder represents an element that does not have a specific path.

• can_carry_signal (bool) –

  Whether this exact object is able to receive, pass or hold signal values.

• instance_type (str) –

  Identifier for instances of this gate type.

• connections (Dict[str, Dict[int, WireSegmentPath]]) –

  A dictionary mapping port names to their corresponding connection paths.

• connection_str_paths (Dict[str, Dict[int, str]]) –

  Returns a dictionary mapping port names to their corresponding connection paths as strings.

• ports (CustomDict[str, Port[Instance]]) –

  A dictionary mapping port names to their corresponding Port objects.

• input_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of input ports associated with this instance.

• output_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of output ports associated with this instance.

• has_unconnected_port_segments (bool) –

  Returns True if the instance has at least one unconnected port segment.

• signals (Dict[str, SignalArray]) –

  A dictionary with all signals currently present on all ports of this instance.

• is_blackbox (bool) –

  Flag indicating whether the instance represents neither a primitive element nor a module instance.

• a_width (PositiveInt) –

  Width of the gate's A port.

• b_width (PositiveInt) –

  Width of the gate's B port.

• is_combinational (bool) –

  Whether instances of this gate are considered combinational gates.

• is_sequential (bool) –

  Whether instances of this gate are considered sequential gates.

• output_port (Port[Instance]) –

  The output port of the gate.

bit_width property writable

bit_width: int

Width of the select/control signal.

y_width property writable

y_width: PositiveInt

Width of the input/data port.

s_defined property

s_defined: bool

Whether all select signal bits are defined.

s_val property

s_val: int

Integer value of the select signals, or -1 if undefined.

active_output property

active_output: Optional[Port[Instance]]

The active output port based on select value.

s_port property

s_port: Port[Instance]

The select/control port.

name instance-attribute

name: str

The name of the element.

!!! Do not modify this variable after instantiating it. Use NetlistElement.set_name() instead. Modifying this variable might lead to inconsistencies later on.

metadata class-attribute instance-attribute

metadata: MetadataMixin = MetadataMixin()

Metadata of a netlist element.

Can be user-defined, or e. g. by Yosys (such as src for the HDL source). Is also grouped by categories, i.e. all metadata from Yosys can be accessed via Module.metadata["yosys"], or via Module.metadata.yosys, which both return a dictionary of all metadata. Read the documentation of MetaDataMixin for more information.

path property

path: InstancePath

Returns the InstancePath of the netlist element.

The InstancePath object is constructed using the element's type and its raw hierarchical path.

Returns:

• InstancePath ( InstancePath ) –

  The hierarchical path of the netlist element.

type property

type: EType

The type of the element, which is an instance.

hierarchy_level property

hierarchy_level: int

The level of hierarchy of the element in the design.

The hierarchy level is the number of separators in the element's raw path. For example, a top-level instance has a hierarchy level of 0, while a direct submodule instance has a hierarchy level of 1.

Returns:

• int ( int ) –

  The hierarchy level of the element.

has_parent property

has_parent: bool

Whether this object has a parent.

circuit property

circuit: 'Circuit'

The circuit object to which this netlist element belongs to.

• For a module, returns the circuit to which the module belongs.
• For any other netlist element, recursively returns the circuit of the parent, which ultimately leads to a module, to which the netlist element belongs.

Raises:

• ParentNotFoundError –

  If a parent cannot be resolved somewhere in the hierarchical chain.

• ObjectNotFoundError –

  If for a module no circuit is set.

has_circuit property

has_circuit: bool

Whether this netlist element has a defined circuit it belongs to.

Tries to access self.circuit and returns whether the call was successful. Can be used instead of a try-except clause around the call to NetlistElement.circuit.

locked property

locked: bool

True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

Can be changed via NetlistElement.change_mutability(bool).

Immutability is used to prevent accidental changes to the design.

is_placeholder_instance property

is_placeholder_instance: bool

A placeholder represents an element that does not have a specific path.

True if this NetlistElement instance represents a placeholder, False otherwise.

can_carry_signal property

can_carry_signal: bool

Whether this exact object is able to receive, pass or hold signal values.

True for ports (as they drive or receive values) and wires (as they pass the signals from driver to load ports) as well as their respective segments. False for instances and modules.

instance_type class-attribute instance-attribute

instance_type: str = CFG.id_internal

Identifier for instances of this gate type.

connections property

connections: Dict[str, Dict[int, WireSegmentPath]]

A dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port. Elements with no connection (i.e. the path is None) are excluded. In case these are needed, use Instance.get_connections() instead.

Example

{ 'port1': {1: WireSegmentPath('path/to/element1'), 2: WireSegmentPath('path/to/element2')}, 'port2': {1: WireSegmentPath('path/to/element3')} }

connection_str_paths property

connection_str_paths: Dict[str, Dict[int, str]]

Returns a dictionary mapping port names to their corresponding connection paths as strings.

The keys are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are the raw string paths.

Example

{ 'port1': {0: 'path.to.element1', 1: 'path.to.element2'}, 'port2': {0: 'path.to.element3'} }

ports property

ports: CustomDict[str, Port[Instance]]

A dictionary mapping port names to their corresponding Port objects.

The keys of the dictionary are the names of the ports. The values are Port objects representing the ports.

Returns:

• CustomDict[str, Port[Instance]] –

  A dictionary mapping port names to their corresponding Port objects.

input_ports property

input_ports: Tuple[Port[Instance], ...]

Returns a tuple of input ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as inputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the input ports.

output_ports property

output_ports: Tuple[Port[Instance], ...]

Returns a tuple of output ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as outputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the output ports.

has_unconnected_port_segments property

has_unconnected_port_segments: bool

Returns True if the instance has at least one unconnected port segment.

signals property

signals: Dict[str, SignalArray]

A dictionary with all signals currently present on all ports of this instance.

is_blackbox property

is_blackbox: bool

Flag indicating whether the instance represents neither a primitive element nor a module instance.

If True, this instance does not have a module definition, and is also not a basic component (i.e. a primitive gate instance) from the internal gate library, such as a gate or flip-flop.

a_width property

a_width: PositiveInt

Width of the gate's A port.

b_width property

b_width: PositiveInt

Width of the gate's B port.

is_combinational property

is_combinational: bool

Whether instances of this gate are considered combinational gates.

True for combinational gates, such as AND gates or arithmetic gates. False for flip-flops and latches.

is_sequential property

is_sequential: bool

Whether instances of this gate are considered sequential gates.

False for combinational gates, such as AND gates or arithmetic gates. True for flip-flops and latches.

output_port property

output_port: Port[Instance]

The output port of the gate.

change_mutability

change_mutability(is_now_locked: bool, recursive: bool = False) -> Self

Change the mutability status of this instance and optionally its ports.

This method allows setting whether this instance can be modified or not. If recursive is set to True, it also applies the same mutability status to all ports of this instance.

Parameters:

• is_now_locked

  (bool) –

  The new mutability status for this instance.

• recursive

  (bool, default: False ) –

  Whether to apply the change recursively to its ports. Defaults to False.

evaluate

evaluate() -> None

Evaluates the gate's output signal based on its input signals.

This method is called when the gate's input signals change, and it updates the gate's output signal accordingly.

all_connections

all_connections(
    include_unconnected: bool,
) -> Dict[str, Dict[int, WireSegmentPath]]

Returns a dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port.

Parameters:

• include_unconnected

  (bool) –

  Whether to include unconnected ports in the result.

Returns:

• Dict[str, Dict[int, WireSegmentPath]] –

  A dictionary mapping port names to their corresponding connection paths.

connect

connect(
    port_name: str,
    ws_path: Optional[WireSegmentPath],
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add connections to the specified port of this instance.

This method can establish multiple connections if a range of indices is provided.

Parameters:

• port_name

  (str) –

  The name of the port where the connection(s) should be established.

• ws_path

  (Optional[WireSegmentPath]) –

  The path of the wire segment that will be connected to this port. If None, the associated port (segment) remains unconnected.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

Raises:

• ObjectLockedError –

  If this instance is currently locked, and no connection can be made.

disconnect

disconnect(port_name: str, index: Optional[int] = None) -> None

Remove an existing connection from a specified port of this instance.

This method disconnects the wire segment at the given index within the specified port_name.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be removed.

• index

  (Optional[int], default: None ) –

  The bit index within the port for this disconnection. Defaults to None, which completely disconnects the port.

Raises:

• ObjectLockedError –

  If this instance is locked.

• ObjectNotFoundError –

  If no port exists with the given name.

get_connection

get_connection(
    port_name: str, index: Optional[NonNegativeInt] = None
) -> Union[WireSegmentPath, Dict[int, WireSegmentPath], None]

Retrieve the connection path associated with a specified port and bit index.

If index is provided, this method returns the wire segment path connected to that specific bit within the port. Otherwise, it returns all connections for the given port as a dictionary mapping indices to WireSegmentPaths.

Parameters:

• port_name

  (str) –

  The name of the port for which to retrieve the connection(s).

• index

  (Optional[NonNegativeInt], default: None ) –

  The bit index within the port. Defaults to None.

Returns:

• Union[WireSegmentPath, Dict[int, WireSegmentPath], None] –

  Union[WireSegmentPath, Dict[int, WireSegmentPath]]: Either a single WireSegmentPath or a dictionary mapping indices to WireSegmentPaths.

modify_connection

modify_connection(
    port_name: str, ws_path: WireSegmentPath, index: NonNegativeInt = 0
) -> None

Modify an existing connection within a specified port of this instance.

This method updates the wire segment path at the given index within the specified port_name. If the index does not exist yet, it is newly added, changing the width of the port.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be modified.

• ws_path

  (WireSegmentPath) –

  The new wire segment path for this connection.

• index

  (NonNegativeInt, default: 0 ) –

  The bit index within the port. Defaults to 0.

connect_modify

connect_modify(
    port_name: str,
    ws_path: WireSegmentPath,
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add a new connection or modify an existing one within the specified port of this instance.

If the connection already exists at the given index and port_name, it will be modified. Otherwise, a new connection is added.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be established or updated.

• ws_path

  (WireSegmentPath) –

  The path of the wire segment that will be connected to this port.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

tie_port

tie_port(name: str, index: NonNegativeInt, sig_value: LogicLevel) -> None

Set a constant signal value for the specified port and bit index.

If the specified port does not exist, an error message is logged and the function returns False. Otherwise, the method tries to set the constant signal value for that port and returns True if successful.

Does not work for instance output ports, as they are always driven by their parent instances.

Parameters:

• name

  (str) –

  The name of the port.

• index

  (NonNegativeInt) –

  The bit index within the port.

• sig_value

  (LogicLevel) –

  The constant signal value to be set ('0', '1', or 'Z').

Raises:

• ObjectNotFoundError –

  If no such port or port segment exists.

• AlreadyConnectedError –

  (raised by: PortSegment.tie_signal) If this segment is belongs to a load port and is already connected to a wire, from which it receives its value.

• InvalidDirectionError –

  (raised by: PortSegment.tie_signal) If this port segment belongs to an instance output port, which is driven by the instance inputs and the instance's internal logic.

• InvalidSignalError –

  (raised by: PortSegment.tie_signal) If an invalid value is provided.

has_tied_ports

has_tied_ports() -> bool

Checks the ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any ports of this instance are tied to constant values. False otherwise, i.e. all ports are connected to wires.

has_tied_inputs

has_tied_inputs() -> bool

Checks the input ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any input ports of this instance are tied to constant values. False otherwise, i.e. all input ports are connected to wires.

has_tied_outputs

has_tied_outputs() -> bool

Checks the output ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any output ports of this instance are tied to constant values. False otherwise, i.e. all output ports are connected to wires.

update_signedness

update_signedness(port_name: str) -> None

Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

Parameters:

• port_name

  (str) –

  The name of the port, of which the signedness value is retrieved.

split

split() -> Dict[NonNegativeInt, Self]

Performs a bit-wise split on this instance.

If this instance supports splitting and has a data width of n bit, this method splits this instance into n 1-bit instances. This works for instances, where each output bit depends only on the corresponding input bit(s), e.g. an AND gate or a D-Flipflop.

Returns:

• Dict[NonNegativeInt, Self] –

  Dict[int, Instance]: An n-bit large dictionary, where each key conforms to a bit of the original instance, and each value is an 1-bit instance representing the corresponding "slice" of the original instance.

Raises:

• SplittingUnsupportedError –

  If this instance does not support splitting. Happens for any gate or instance whose behavior depends on the whole bus, and splitting would make it lose its meaning.

p2v

p2v(
    port: ANY_PORT,
    exclude_indices: Optional[List[int]] = None,
    include_indices: Optional[List[int]] = None,
) -> str

Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a Port object and converts them to their corresponding Verilog signal structure (p2v -> Port to Verilog signal syntax). For each segment of the port, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port is set to a constant, the corresponding constant wire segment placeholder is used instead. Port segments can be excluded from the conversion by providing a list of indices to the exclude_indices parameter, indicating which segments should be excluded from the conversion (e.g. segments that are known to be unconnected). Vice versa, only a certain subset of the port's segments may be converted to Verilog syntax, if include_indices is a given list of port indices. All indices not present in the list will be excluded from the conversion.

Parameters:

• port

  (Port) –

  The Port object to convert.

• exclude_indices

  (List[int], default: None ) –

  A list of indices to exclude from the conversion. Defaults to None.

• include_indices

  (List[int], default: None ) –

  A list of indices (i.e. port slices) to include only for the conversion. Defaults to None.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

ps2v

ps2v(ps_dict: Dict[int, PortSegment]) -> str

Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a PortSegment dictionary and converts them to their corresponding Verilog signal structure (ps2v -> PortSegment to Verilog signal syntax). For each segment, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port segment is set to a constant, the corresponding constant wire segment placeholder is used instead.

Parameters:

• ps_dict

  (Dict[int, PortSegment]) –

  The PortSegment dictionary to convert. Each key (int) conforms to the index of the associated PortSegment object.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

• UnsupportedOperationError –

  If two segments belong to different modules.

set

set(
    port_name: str,
    new_signal: SignalOrLogicLevel,
    idx: Union[int, List[int]] = 0,
) -> None

Sets the signal on a port.

Parameters:

• port_name

  (str) –

  The name of the port to set the signal on.

• new_signal

  (Signal) –

  The new signal value.

• idx

  (Union[int, List[int]], default: 0 ) –

  The index (or indices) to apply the given signal to. Can either be an integer (single index to set) or an iterable of integers (e.g. a list of indices). For every integer of the iterable the signal value of the corresponding port index is set to the given new_signal. Defaults to 0.

Example

from netlist_carpentry.utils.gate_factory import and_gate module = Module(name='m') a = module.create_port('a', 'input', width=6) instance = and_gate(module, 'inst', A=a)

This sets the value of bit 0 of port A to HIGH

instance.set('A', 1, 0) instance.ports['A'].signal_str 'xxxxx1'

This sets the value of bits 1, 3 and 5 of port A to LOW, leaving the other bits as they already are.

instance.set('A', 0, [1, 3, 5]) instance.ports['A'].signal_str '0x0x01'

StorageGate

Bases: PrimitiveGate, BaseModel

Methods:

• model_post_init –

  Initializes the gate's ports and connections.

• change_mutability –

  Change the mutability status of this instance and optionally its ports.

• evaluate –

  Evaluates the gate's output signal based on its input signals.

• all_connections –

  Returns a dictionary mapping port names to their corresponding connection paths.

• connect –

  Add connections to the specified port of this instance.

• disconnect –

  Remove an existing connection from a specified port of this instance.

• get_connection –

  Retrieve the connection path associated with a specified port and bit index.

• modify_connection –

  Modify an existing connection within a specified port of this instance.

• connect_modify –

  Add a new connection or modify an existing one within the specified port of this instance.

• tie_port –

  Set a constant signal value for the specified port and bit index.

• has_tied_ports –

  Checks the ports of this instance whether any are tied to constant values.

• has_tied_inputs –

  Checks the input ports of this instance whether any are tied to constant values.

• has_tied_outputs –

  Checks the output ports of this instance whether any are tied to constant values.

• update_signedness –

  Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

• split –

  Performs a bit-wise split on this instance.

• p2v –

  Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

• ps2v –

  Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

• set –

  Sets the signal on a port.

Attributes:

• input_port (Port[Instance]) –

  The input port of the gate.

• output_port (Port[Instance]) –

  The output port of the gate.

• name (str) –

  The name of the element.

• metadata (MetadataMixin) –

  Metadata of a netlist element.

• path (InstancePath) –

  Returns the InstancePath of the netlist element.

• type (EType) –

  The type of the element, which is an instance.

• hierarchy_level (int) –

  The level of hierarchy of the element in the design.

• has_parent (bool) –

  Whether this object has a parent.

• circuit ('Circuit') –

  The circuit object to which this netlist element belongs to.

• has_circuit (bool) –

  Whether this netlist element has a defined circuit it belongs to.

• locked (bool) –

  True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

• is_placeholder_instance (bool) –

  A placeholder represents an element that does not have a specific path.

• can_carry_signal (bool) –

  Whether this exact object is able to receive, pass or hold signal values.

• instance_type (str) –

  Identifier for instances of this gate type.

• connections (Dict[str, Dict[int, WireSegmentPath]]) –

  A dictionary mapping port names to their corresponding connection paths.

• connection_str_paths (Dict[str, Dict[int, str]]) –

  Returns a dictionary mapping port names to their corresponding connection paths as strings.

• ports (CustomDict[str, Port[Instance]]) –

  A dictionary mapping port names to their corresponding Port objects.

• input_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of input ports associated with this instance.

• output_ports (Tuple[Port[Instance], ...]) –

  Returns a tuple of output ports associated with this instance.

• has_unconnected_port_segments (bool) –

  Returns True if the instance has at least one unconnected port segment.

• signals (Dict[str, SignalArray]) –

  A dictionary with all signals currently present on all ports of this instance.

• is_blackbox (bool) –

  Flag indicating whether the instance represents neither a primitive element nor a module instance.

• verilog (str) –

  Generates the Verilog code for this instance.

• a_width (PositiveInt) –

  Width of the gate's A port.

• b_width (PositiveInt) –

  Width of the gate's B port.

• is_sequential (bool) –

  Whether instances of this gate are considered sequential gates.

• data_width (int) –

  The data width of this instance.

input_port property

input_port: Port[Instance]

The input port of the gate.

output_port property

output_port: Port[Instance]

The output port of the gate.

name instance-attribute

name: str

The name of the element.

!!! Do not modify this variable after instantiating it. Use NetlistElement.set_name() instead. Modifying this variable might lead to inconsistencies later on.

metadata class-attribute instance-attribute

metadata: MetadataMixin = MetadataMixin()

Metadata of a netlist element.

Can be user-defined, or e. g. by Yosys (such as src for the HDL source). Is also grouped by categories, i.e. all metadata from Yosys can be accessed via Module.metadata["yosys"], or via Module.metadata.yosys, which both return a dictionary of all metadata. Read the documentation of MetaDataMixin for more information.

path property

path: InstancePath

Returns the InstancePath of the netlist element.

The InstancePath object is constructed using the element's type and its raw hierarchical path.

Returns:

• InstancePath ( InstancePath ) –

  The hierarchical path of the netlist element.

type property

type: EType

The type of the element, which is an instance.

hierarchy_level property

hierarchy_level: int

The level of hierarchy of the element in the design.

The hierarchy level is the number of separators in the element's raw path. For example, a top-level instance has a hierarchy level of 0, while a direct submodule instance has a hierarchy level of 1.

Returns:

• int ( int ) –

  The hierarchy level of the element.

has_parent property

has_parent: bool

Whether this object has a parent.

circuit property

circuit: 'Circuit'

The circuit object to which this netlist element belongs to.

• For a module, returns the circuit to which the module belongs.
• For any other netlist element, recursively returns the circuit of the parent, which ultimately leads to a module, to which the netlist element belongs.

Raises:

• ParentNotFoundError –

  If a parent cannot be resolved somewhere in the hierarchical chain.

• ObjectNotFoundError –

  If for a module no circuit is set.

has_circuit property

has_circuit: bool

Whether this netlist element has a defined circuit it belongs to.

Tries to access self.circuit and returns whether the call was successful. Can be used instead of a try-except clause around the call to NetlistElement.circuit.

locked property

locked: bool

True if this NetlistElement instance is locked (i.e. it is currently structurally unchangeable), False if it is mutable.

Can be changed via NetlistElement.change_mutability(bool).

Immutability is used to prevent accidental changes to the design.

is_placeholder_instance property

is_placeholder_instance: bool

A placeholder represents an element that does not have a specific path.

True if this NetlistElement instance represents a placeholder, False otherwise.

can_carry_signal property

can_carry_signal: bool

Whether this exact object is able to receive, pass or hold signal values.

True for ports (as they drive or receive values) and wires (as they pass the signals from driver to load ports) as well as their respective segments. False for instances and modules.

instance_type class-attribute instance-attribute

instance_type: str = CFG.id_internal

Identifier for instances of this gate type.

connections property

connections: Dict[str, Dict[int, WireSegmentPath]]

A dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port. Elements with no connection (i.e. the path is None) are excluded. In case these are needed, use Instance.get_connections() instead.

Example

{ 'port1': {1: WireSegmentPath('path/to/element1'), 2: WireSegmentPath('path/to/element2')}, 'port2': {1: WireSegmentPath('path/to/element3')} }

connection_str_paths property

connection_str_paths: Dict[str, Dict[int, str]]

Returns a dictionary mapping port names to their corresponding connection paths as strings.

The keys are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are the raw string paths.

Example

{ 'port1': {0: 'path.to.element1', 1: 'path.to.element2'}, 'port2': {0: 'path.to.element3'} }

ports property

ports: CustomDict[str, Port[Instance]]

A dictionary mapping port names to their corresponding Port objects.

The keys of the dictionary are the names of the ports. The values are Port objects representing the ports.

Returns:

• CustomDict[str, Port[Instance]] –

  A dictionary mapping port names to their corresponding Port objects.

input_ports property

input_ports: Tuple[Port[Instance], ...]

Returns a tuple of input ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as inputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the input ports.

output_ports property

output_ports: Tuple[Port[Instance], ...]

Returns a tuple of output ports associated with this instance.

This property filters the ports based on their direction, returning only those that are marked as outputs.

Returns:

• Tuple[Port[Instance], ...] –

  A tuple of Port objects representing the output ports.

has_unconnected_port_segments property

has_unconnected_port_segments: bool

Returns True if the instance has at least one unconnected port segment.

signals property

signals: Dict[str, SignalArray]

A dictionary with all signals currently present on all ports of this instance.

is_blackbox property

is_blackbox: bool

Flag indicating whether the instance represents neither a primitive element nor a module instance.

If True, this instance does not have a module definition, and is also not a basic component (i.e. a primitive gate instance) from the internal gate library, such as a gate or flip-flop.

verilog property

verilog: str

Generates the Verilog code for this instance.

This property uses the verilog_template to generate the actual Verilog code by replacing the placeholders with the instance type, name, and port connections. It returns a string that can be used directly in a Verilog file.

Returns:

• str ( str ) –

  The generated Verilog code.

a_width property

a_width: PositiveInt

Width of the gate's A port.

b_width property

b_width: PositiveInt

Width of the gate's B port.

is_sequential property

is_sequential: bool

Whether instances of this gate are considered sequential gates.

False for combinational gates, such as AND gates or arithmetic gates. True for flip-flops and latches.

data_width property

data_width: int

The data width of this instance.

Defaults to the data width of the output port. Can be overwritten in extended classes.

In contrast to self.width, which is used for the creation and initialization, this property is linked to the data width of the output port. This property is useful when the data width of the output port can be changed.

model_post_init

model_post_init(__context: object) -> None

Initializes the gate's ports and connections.

This method is called after the gate's attributes have been initialized, and it sets up the gate's ports and connections.

change_mutability

change_mutability(is_now_locked: bool, recursive: bool = False) -> Self

Change the mutability status of this instance and optionally its ports.

This method allows setting whether this instance can be modified or not. If recursive is set to True, it also applies the same mutability status to all ports of this instance.

Parameters:

• is_now_locked

  (bool) –

  The new mutability status for this instance.

• recursive

  (bool, default: False ) –

  Whether to apply the change recursively to its ports. Defaults to False.

evaluate

evaluate() -> None

Evaluates the gate's output signal based on its input signals.

This method is called when the gate's input signals change, and it updates the gate's output signal accordingly.

all_connections

all_connections(
    include_unconnected: bool,
) -> Dict[str, Dict[int, WireSegmentPath]]

Returns a dictionary mapping port names to their corresponding connection paths.

The keys of the outer dictionary are the names of the ports. The values are dictionaries where the keys are the port bit numbers and the values are WireSegmentPath objects. The element paths are the paths of the wires connected to the corresponding bits of the port.

Parameters:

• include_unconnected

  (bool) –

  Whether to include unconnected ports in the result.

Returns:

• Dict[str, Dict[int, WireSegmentPath]] –

  A dictionary mapping port names to their corresponding connection paths.

connect

connect(
    port_name: str,
    ws_path: Optional[WireSegmentPath],
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add connections to the specified port of this instance.

This method can establish multiple connections if a range of indices is provided.

Parameters:

• port_name

  (str) –

  The name of the port where the connection(s) should be established.

• ws_path

  (Optional[WireSegmentPath]) –

  The path of the wire segment that will be connected to this port. If None, the associated port (segment) remains unconnected.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

Raises:

• ObjectLockedError –

  If this instance is currently locked, and no connection can be made.

disconnect

disconnect(port_name: str, index: Optional[int] = None) -> None

Remove an existing connection from a specified port of this instance.

This method disconnects the wire segment at the given index within the specified port_name.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be removed.

• index

  (Optional[int], default: None ) –

  The bit index within the port for this disconnection. Defaults to None, which completely disconnects the port.

Raises:

• ObjectLockedError –

  If this instance is locked.

• ObjectNotFoundError –

  If no port exists with the given name.

get_connection

get_connection(
    port_name: str, index: Optional[NonNegativeInt] = None
) -> Union[WireSegmentPath, Dict[int, WireSegmentPath], None]

Retrieve the connection path associated with a specified port and bit index.

If index is provided, this method returns the wire segment path connected to that specific bit within the port. Otherwise, it returns all connections for the given port as a dictionary mapping indices to WireSegmentPaths.

Parameters:

• port_name

  (str) –

  The name of the port for which to retrieve the connection(s).

• index

  (Optional[NonNegativeInt], default: None ) –

  The bit index within the port. Defaults to None.

Returns:

• Union[WireSegmentPath, Dict[int, WireSegmentPath], None] –

  Union[WireSegmentPath, Dict[int, WireSegmentPath]]: Either a single WireSegmentPath or a dictionary mapping indices to WireSegmentPaths.

modify_connection

modify_connection(
    port_name: str, ws_path: WireSegmentPath, index: NonNegativeInt = 0
) -> None

Modify an existing connection within a specified port of this instance.

This method updates the wire segment path at the given index within the specified port_name. If the index does not exist yet, it is newly added, changing the width of the port.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be modified.

• ws_path

  (WireSegmentPath) –

  The new wire segment path for this connection.

• index

  (NonNegativeInt, default: 0 ) –

  The bit index within the port. Defaults to 0.

connect_modify

connect_modify(
    port_name: str,
    ws_path: WireSegmentPath,
    direction: Direction = UNKNOWN,
    index: NonNegativeInt = 0,
    width: PositiveInt = 1,
) -> None

Add a new connection or modify an existing one within the specified port of this instance.

If the connection already exists at the given index and port_name, it will be modified. Otherwise, a new connection is added.

Parameters:

• port_name

  (str) –

  The name of the port where the connection should be established or updated.

• ws_path

  (WireSegmentPath) –

  The path of the wire segment that will be connected to this port.

• direction

  (Direction, default: UNKNOWN ) –

  The direction of the port. Defaults to Direction.UNKNOWN.

• index

  (NonNegativeInt, default: 0 ) –

  The starting bit index within the port for these connections. Defaults to 0.

• width

  (PositiveInt, default: 1 ) –

  The number of consecutive bits in the port that should be connected. Defaults to 1.

tie_port

tie_port(name: str, index: NonNegativeInt, sig_value: LogicLevel) -> None

Set a constant signal value for the specified port and bit index.

If the specified port does not exist, an error message is logged and the function returns False. Otherwise, the method tries to set the constant signal value for that port and returns True if successful.

Does not work for instance output ports, as they are always driven by their parent instances.

Parameters:

• name

  (str) –

  The name of the port.

• index

  (NonNegativeInt) –

  The bit index within the port.

• sig_value

  (LogicLevel) –

  The constant signal value to be set ('0', '1', or 'Z').

Raises:

• ObjectNotFoundError –

  If no such port or port segment exists.

• AlreadyConnectedError –

  (raised by: PortSegment.tie_signal) If this segment is belongs to a load port and is already connected to a wire, from which it receives its value.

• InvalidDirectionError –

  (raised by: PortSegment.tie_signal) If this port segment belongs to an instance output port, which is driven by the instance inputs and the instance's internal logic.

• InvalidSignalError –

  (raised by: PortSegment.tie_signal) If an invalid value is provided.

has_tied_ports

has_tied_ports() -> bool

Checks the ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any ports of this instance are tied to constant values. False otherwise, i.e. all ports are connected to wires.

has_tied_inputs

has_tied_inputs() -> bool

Checks the input ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any input ports of this instance are tied to constant values. False otherwise, i.e. all input ports are connected to wires.

has_tied_outputs

has_tied_outputs() -> bool

Checks the output ports of this instance whether any are tied to constant values.

Instance ports can be tied to a constant value for several reasons, but if all input or all output ports are tied, the instance is rendered useless.

Returns:

• bool ( bool ) –

  True if any output ports of this instance are tied to constant values. False otherwise, i.e. all output ports are connected to wires.

update_signedness

update_signedness(port_name: str) -> None

Retrieves the signedness of the given port and updates it in this gate instance's parameter dictionary.

Parameters:

• port_name

  (str) –

  The name of the port, of which the signedness value is retrieved.

split

split() -> Dict[NonNegativeInt, Self]

Performs a bit-wise split on this instance.

If this instance supports splitting and has a data width of n bit, this method splits this instance into n 1-bit instances. This works for instances, where each output bit depends only on the corresponding input bit(s), e.g. an AND gate or a D-Flipflop.

Returns:

• Dict[NonNegativeInt, Self] –

  Dict[int, Instance]: An n-bit large dictionary, where each key conforms to a bit of the original instance, and each value is an 1-bit instance representing the corresponding "slice" of the original instance.

Raises:

• SplittingUnsupportedError –

  If this instance does not support splitting. Happens for any gate or instance whose behavior depends on the whole bus, and splitting would make it lose its meaning.

p2v

p2v(
    port: ANY_PORT,
    exclude_indices: Optional[List[int]] = None,
    include_indices: Optional[List[int]] = None,
) -> str

Converts a Port object to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a Port object and converts them to their corresponding Verilog signal structure (p2v -> Port to Verilog signal syntax). For each segment of the port, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port is set to a constant, the corresponding constant wire segment placeholder is used instead. Port segments can be excluded from the conversion by providing a list of indices to the exclude_indices parameter, indicating which segments should be excluded from the conversion (e.g. segments that are known to be unconnected). Vice versa, only a certain subset of the port's segments may be converted to Verilog syntax, if include_indices is a given list of port indices. All indices not present in the list will be excluded from the conversion.

Parameters:

• port

  (Port) –

  The Port object to convert.

• exclude_indices

  (List[int], default: None ) –

  A list of indices to exclude from the conversion. Defaults to None.

• include_indices

  (List[int], default: None ) –

  A list of indices (i.e. port slices) to include only for the conversion. Defaults to None.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

ps2v

ps2v(ps_dict: Dict[int, PortSegment]) -> str

Converts a PortSegment dictionary to its corresponding Verilog structure by using the connected wire segments.

This method takes the connected wire segments of a PortSegment dictionary and converts them to their corresponding Verilog signal structure (ps2v -> PortSegment to Verilog signal syntax). For each segment, it checks whether a corresponding connected wire segment exists in the corresponding module. If the port segment is set to a constant, the corresponding constant wire segment placeholder is used instead.

Parameters:

• ps_dict

  (Dict[int, PortSegment]) –

  The PortSegment dictionary to convert. Each key (int) conforms to the index of the associated PortSegment object.

Returns:

• str ( str ) –

  The Verilog signal structure as a string, e.g. some_wire[3:0] or {w, 2'b01}.

Raises:

• ObjectNotFoundError –

  If the wire connected to a certain port segment could not be found.

• UnsupportedOperationError –

  If both exclude_indices and include_indices are specified. Only one of both may be given when calling this method.

• UnsupportedOperationError –

  If two segments belong to different modules.

set

set(
    port_name: str,
    new_signal: SignalOrLogicLevel,
    idx: Union[int, List[int]] = 0,
) -> None

Sets the signal on a port.

Parameters:

• port_name

  (str) –

  The name of the port to set the signal on.

• new_signal

  (Signal) –

  The new signal value.

• idx

  (Union[int, List[int]], default: 0 ) –

  The index (or indices) to apply the given signal to. Can either be an integer (single index to set) or an iterable of integers (e.g. a list of indices). For every integer of the iterable the signal value of the corresponding port index is set to the given new_signal. Defaults to 0.

Example

from netlist_carpentry.utils.gate_factory import and_gate module = Module(name='m') a = module.create_port('a', 'input', width=6) instance = and_gate(module, 'inst', A=a)

This sets the value of bit 0 of port A to HIGH

instance.set('A', 1, 0) instance.ports['A'].signal_str 'xxxxx1'

This sets the value of bits 1, 3 and 5 of port A to LOW, leaving the other bits as they already are.

instance.set('A', 0, [1, 3, 5]) instance.ports['A'].signal_str '0x0x01'