netlist_carpentry.utils.gate_lib_dataclasses
¶
Module for typed dictionaries used throughout the gate library for convenience.
Classes:
-
Parameters– -
WireParams–Common parameters for Wires.
-
UnaryParams–Common parameters for Unary cells and derived classes.
-
BinaryParams–Common parameters for Binary cells and derived classes.
-
MuxParams–Common parameters for Muxes and Demuxes.
-
DFFParams–Common parameters for DFFs and derived classes.
-
DLatchParams–Common parameters for DLatches.
-
MemoryParams–
Parameters
¶
WireParams
¶
Bases: Parameters
Common parameters for Wires.
Methods:
-
as_dict–Returns this parameter set as a dictionary.
-
items–Returns the parameter names and values as a list of tuples.
as_dict
¶
UnaryParams
¶
BinaryParams
¶
MuxParams
¶
DFFParams
¶
DLatchParams
¶
MemoryParams
¶
Bases: ClockParams, EnableParams
Methods:
-
as_dict–Returns this parameter set as a dictionary.
-
items–Returns the parameter names and values as a list of tuples.
Attributes:
-
MEMID(Optional[str]) –The name of the original object that became this mem_v2 cell.
-
SIZE(Optional[PositiveInt]) –The number of words in the memory.
-
WIDTH(Optional[PositiveInt]) –The number of address bits.
-
ABITS(Optional[PositiveInt]) –The number of data bits per word.
-
OFFSET(Optional[PositiveInt]) –The address offset.
-
INIT(Optional[SignalArray]) –The initial memory contents.
-
RD_PORTS(Optional[PositiveInt]) –The number of read ports on this memory cell.
-
RD_CE_OVER_SRST(Optional[SignalArray]) –This parameter is
RD_PORTSbits wide, determining relative synchronous reset and enable priority for each read port. -
RD_CLK_ENABLE(Optional[SignalArray]) –This parameter is
RD_PORTSbits wide, containing a clock enable bit for each read port. -
RD_CLK_POLARITY(Optional[SignalArray]) –This parameter is
RD_PORTSbits wide, containing a clock polarity bit for each read port. -
RD_COLLISION_X_MASK(Optional[SignalArray]) –This parameter is
RD_PORTS*WR_PORTSbits wide, containing a concatenation of all COLLISION_X_MASK values of the original memrd cells. -
RD_INIT_VALUE(Optional[SignalArray]) –This parameter is
RD_PORTS*WIDTHbits wide, containing the initial value for each synchronous read port. -
RD_TRANSPARENCY_MASK(Optional[SignalArray]) –This parameter is
RD_PORTS*WR_PORTSbits wide, containing a concatenation of all TRANSPARENCY_MASK values of the original memrd cells. -
RD_WIDE_CONTINUATION(Optional[SignalArray]) –This parameter is
RD_PORTSbits wide, containing a bitmask of "wide continuation" read ports. -
WR_PORTS(Optional[PositiveInt]) –The number of read ports on this memory cell.
-
WR_CLK_ENABLE(Optional[SignalArray]) –This parameter is
WR_PORTSbits wide, containing a clock enable bit for each write port. -
WR_CLK_POLARITY(Optional[SignalArray]) –This parameter is
WR_PORTSbits wide, containing a clock polarity bit for each write port. -
WR_PRIORITY_MASK(Optional[SignalArray]) –This parameter is
WR_PORTS*WR_PORTSbits wide, containing a concatenation of all PRIORITY_MASK values of the original memwr cells. -
WR_WIDE_CONTINUATION(Optional[SignalArray]) –This parameter is
WR_PORTSbits wide, containing a bitmask of "wide continuation" write ports.
MEMID
class-attribute
instance-attribute
¶
The name of the original object that became this mem_v2 cell.
SIZE
class-attribute
instance-attribute
¶
SIZE: Optional[PositiveInt] = None
The number of words in the memory.
WIDTH
class-attribute
instance-attribute
¶
WIDTH: Optional[PositiveInt] = None
The number of address bits.
ABITS
class-attribute
instance-attribute
¶
ABITS: Optional[PositiveInt] = None
The number of data bits per word.
OFFSET
class-attribute
instance-attribute
¶
OFFSET: Optional[PositiveInt] = None
The address offset.
INIT
class-attribute
instance-attribute
¶
INIT: Optional[SignalArray] = None
The initial memory contents.
RD_PORTS
class-attribute
instance-attribute
¶
RD_PORTS: Optional[PositiveInt] = None
The number of read ports on this memory cell.
RD_CE_OVER_SRST
class-attribute
instance-attribute
¶
RD_CE_OVER_SRST: Optional[SignalArray] = None
This parameter is RD_PORTS bits wide, determining relative synchronous reset and enable priority for each read port.
RD_CLK_ENABLE
class-attribute
instance-attribute
¶
RD_CLK_ENABLE: Optional[SignalArray] = None
This parameter is RD_PORTS bits wide, containing a clock enable bit for each read port.
RD_CLK_POLARITY
class-attribute
instance-attribute
¶
RD_CLK_POLARITY: Optional[SignalArray] = None
This parameter is RD_PORTS bits wide, containing a clock polarity bit for each read port.
RD_COLLISION_X_MASK
class-attribute
instance-attribute
¶
RD_COLLISION_X_MASK: Optional[SignalArray] = None
This parameter is RD_PORTS*WR_PORTS bits wide, containing a concatenation of all COLLISION_X_MASK values of the original memrd cells.
RD_INIT_VALUE
class-attribute
instance-attribute
¶
RD_INIT_VALUE: Optional[SignalArray] = None
This parameter is RD_PORTS*WIDTH bits wide, containing the initial value for each synchronous read port.
RD_TRANSPARENCY_MASK
class-attribute
instance-attribute
¶
RD_TRANSPARENCY_MASK: Optional[SignalArray] = None
This parameter is RD_PORTS*WR_PORTS bits wide, containing a concatenation of all TRANSPARENCY_MASK values of the original memrd cells.
RD_WIDE_CONTINUATION
class-attribute
instance-attribute
¶
RD_WIDE_CONTINUATION: Optional[SignalArray] = None
This parameter is RD_PORTS bits wide, containing a bitmask of "wide continuation" read ports.
Such ports are used to represent the extra data bits of wide ports in the combined cell, and must have all control signals identical with the preceding port, except for address, which must have the proper sub-cell address encoded in the low bits.
WR_PORTS
class-attribute
instance-attribute
¶
WR_PORTS: Optional[PositiveInt] = None
The number of read ports on this memory cell.
WR_CLK_ENABLE
class-attribute
instance-attribute
¶
WR_CLK_ENABLE: Optional[SignalArray] = None
This parameter is WR_PORTS bits wide, containing a clock enable bit for each write port.
WR_CLK_POLARITY
class-attribute
instance-attribute
¶
WR_CLK_POLARITY: Optional[SignalArray] = None
This parameter is WR_PORTS bits wide, containing a clock polarity bit for each write port.
WR_PRIORITY_MASK
class-attribute
instance-attribute
¶
WR_PRIORITY_MASK: Optional[SignalArray] = None
This parameter is WR_PORTS*WR_PORTS bits wide, containing a concatenation of all PRIORITY_MASK values of the original memwr cells.
WR_WIDE_CONTINUATION
class-attribute
instance-attribute
¶
WR_WIDE_CONTINUATION: Optional[SignalArray] = None
This parameter is WR_PORTS bits wide, containing a bitmask of "wide continuation" write ports.
Such ports are used to represent the extra data bits of wide ports in the combined cell, and must have all control signals identical with the preceding port, except for address, which must have the proper sub-cell address encoded in the low bits.