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General Information

Netlist Carpentry is a framework for digital circuit analysis and modification. Verilog designs can be read, modified, analyzed, and written back to Verilog using Netlist Carpentry. Below is a representation of the workflow of Netlist Carpentry1.

Test
Figure 1: Test

More information

All configuration and execution is done in Python. A detailed tutorial with executable code examples in form of Jupyter Notebooks is provided as well, starting with 01. Getting Started.

  1. The synthesis step, where Yosys generates a JSON netlist from Verilog, is also handled by Netlist Carpentry. However, it is also possible to provide custom synthesis scripts, or your own JSON netlist to Netlist Carpentry. ↩