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netlist_carpentry.io.write.py2v

Module handling the Verilog write-out of the internal representation of the circuit.

Classes:

P2VTransformer 

P2VTransformer()

Structure: { "module_name": { "module_name.wire_name.index": WireSegment, ... }, ... }

Purpose: Tracks wire segments that represent constant values (e.g., 1'b0, 1'b1, 1'bz) for Verilog output generation. The nested structure allows efficient lookup of constant wires during Verilog code generation, particularly in _constant_wires2v().

Methods:

  • instance2v –

    Transform a Python object into a Verilog instance.

  • wire_name_and_index_from_str –

    Determine the Verilog wire name for a wire in Verilog syntax.

  • wire_name_and_index –

    Determine the Verilog wire name for a given wire segment path.

  • wire2v –

    Converts a netlist wire to a wire or reg in Verilog syntax, depending on its driving instance.

  • port2v –

    Converts a Python Port object into its corresponding Verilog string, representing a module port.

  • simplify_wire_segments –

    Simplify a list of WireSegments into a Verilog-compatible concatenation.

instance2v 

instance2v(module: Module, instance: Instance) -> str

Transform a Python object into a Verilog instance.

This method takes a Module and an Instance as input, and returns the corresponding Verilog instance.

Parameters:

  • module

    (Module) –

    The parent module of the instance.

  • instance

    (Instance) –

    The instance to be transformed into Verilog.

Returns:

  • str ( str ) –

    The Verilog representation of the instance.

wire_name_and_index_from_str classmethod 

wire_name_and_index_from_str(module: Module, path: str) -> str

Determine the Verilog wire name for a wire in Verilog syntax.

In Verilog, wire names can be represented in several ways: - As a single bit (e.g. wire w; and then using it as w) - As an array of bits (e.g. wire [7:0] w; and then using a single segment as w[3], or multiple segments as {w[3], w[0]})

Parameters:

  • module

    (Module) –

    The parent module.

  • path

    (str) –

    The hierarchical path to the wire segment (i.e. to which wire it belongs).

Returns:

  • str ( str ) –

    The corresponding Verilog wire name for the given constant wire segment.

wire_name_and_index classmethod 

wire_name_and_index(module: Module, wseg_path: WireSegmentPath) -> str

Determine the Verilog wire name for a given wire segment path.

This method takes a Module and a WireSegmentPath representing a wire segment as input, and returns the corresponding Verilog wire name for that wire segment. If the wire segment represents a constant value (e.g., 1'b0, 1'b1), it will return the corresponding constant Verilog representation.

Parameters:

  • module

    (Module) –

    The parent module.

  • wseg_path

    (WireSegmentPath) –

    The WireSegmentPath representing the wire segment path.

Returns:

  • str ( str ) –

    The corresponding Verilog wire name for the given wire segment.

wire2v 

wire2v(module: Module, wire: Wire) -> str

Converts a netlist wire to a wire or reg in Verilog syntax, depending on its driving instance.

Parameters:

  • module

    (Module) –

    The module to which this wire belongs to.

  • wire

    (Wire) –

    The netlist wire to convert.

Returns:

  • str ( str ) –

    The Verilog instantiation of the wire, either as reg or wire.

Example 1 
>>> from netlist_carpentry.core.netlist_elements.module import Module
>>> from netlist_carpentry.core.netlist_elements.wire import Wire
>>> module = Module(name='module1')
>>> wire = Wire(name='wire1', width=8)
>>> module.add_wire(wire)
>>> transformer = P2VTransformer()
>>> print(transformer.wire2v(module, wire))
'wire [7:0] wire1;'
Example 2 
>>> from netlist_carpentry.core.netlist_elements.module import Module
>>> from netlist_carpentry.core.netlist_elements.wire import Wire
>>> from netlist_carpentry.utils.gate_lib import DFF
>>> module = Module(name='module1')
>>> dff = DFF(name='dff1')
>>> wire = Wire(name='wire1', width=8)
>>> module.add_wire(wire)
>>> module.add_instance(dff1)
>>> module.connect(dff.ports['Q'].path, wire[0].path)  # Connect wire to a Flip-Flop -> wire becomes a reg
>>> transformer = P2VTransformer()
>>> print(transformer.wire2v(module, wire))
'reg [7:0] wire1;'

port2v 

port2v(module: Module, port: Port[Module]) -> str

Converts a Python Port object into its corresponding Verilog string, representing a module port.

This method takes into account the direction and width of the port to generate the correct Verilog syntax.

Parameters:

  • module

    (Module) –

    The module to which this port belongs to.

  • port

    (Port) –

    The Port object to be converted.

Returns:

  • str ( str ) –

    The Verilog string representation of the port.

Example

from netlist_carpentry.core.netlist_elements.port import Port port = Port(name='port1', direction='input', width=8) transformer = P2VTransformer() print(transformer.port2v(port)) 'input [7:0] port1'

simplify_wire_segments classmethod 

simplify_wire_segments(module: Module, wire_segments: List[WireSegment]) -> str

Simplify a list of WireSegments into a Verilog-compatible concatenation.

This function takes a list of WireSegments and groups them by their wire name. Then, it sorts the segments within each group in descending order and formats them according to the Verilog syntax for concatenating bits. The resulting string is either a single bit assignment or a concatenated bit assignment.

For example, given a list of WireSegments with indices [3, 1, 0], the function would return '{wire[3], wire[1:0]}'. If there are multiple groups, they will be comma-separated within the concatenation brackets. If the index list matches the full wire in correct order, the indexing is dropped completely, since it is not required.

Parameters:

Returns:

  • str ( str ) –

    A Verilog-compatible string representing the concatenated wire segments.