io
¶
Package to handle input and output of circuit data, i.e. transformation from text files to the internal representation, and back.
Modules:
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read–Interface modules to read circuits from certain formats, e.g. Verilog and Yosys-generated JSON netlists.
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vcd–Package for reading VCD files, analyzing simulation data and extracting heuristics from them.
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write–Interface to write the internal representation to Verilog code.