core.graph.pattern_generator
¶
Generator module used to create pattern objects from given HDL code, circuits, or JSON netlists.
Classes:
-
PatternGenerator–This class is a utility class used to create pattern objects from given HDL code,
This class is a utility class used to create pattern objects from given HDL code, circuits, or JSON netlists.
The method build_from_circuit can be used to create a pattern object by providing
a circuit object, which will be used to find structurally matching subcircuits in a
larger circuit. In addition a replacement circuit object can be passed as well, which
is then used to replace any pattern occurrences in the original circuit.
In this case, both circuits must have the same interface, i.e. the top module must
have the same input/output ports in both circuits.
The methods build_from_verilog and build_from_yosys_netlist work analogously,
where the pattern and replacement circuits are either specified in Verilog code,
or as Yosys-generated JSON netlists.
Methods:
-
build_from_circuit–Builds a Pattern instance from Verilog files.
-
build_from_verilog–Builds a Pattern instance from Verilog files.
-
build_from_yosys_netlists–Builds a Pattern instance from Yosys netlist files.
classmethod
¶
build_from_circuit(
match_circuit: Circuit,
replacement_circuit: Circuit = Circuit(name=""),
remove_ports: bool = True,
ignore_port_names: bool = False,
constraints: List[Constraint] = [],
) -> Pattern
Builds a Pattern instance from Verilog files.
Parameters:
-
(match_circuit¶Circuit) –The circuit object representing the structure to find.
-
(replacement_circuit¶Circuit, default:Circuit(name='')) –The circuit object representing the replacement structure. If not specified, the pattern can only be used for analysis and not for modification. Defaults to ''.
-
(remove_ports¶bool, default:True) –Whether to remove all input and output ports of the patterns. Defaults to True. If set to True, all ports are removed, and only the instances inside the module (and the connections between them) are used as pattern. If set to False, the graph of the given modules is used directly, including its module ports. The matching algorithm will then only find matches, if the whole structure (including the module ports) is found!
-
(ignore_port_names¶bool, default:False) –Whether to check port names when trying to match the pattern against found instances. Defaults to False, in which case all port names must match the given pattern.
-
(constraints¶List[Constraint], default:[]) –List of constraints that need to be satisfied by any matching subgraphs. Defaults to [], which means no constraints are applied.
Returns:
-
Pattern(Pattern) –A Pattern instance representing the specified subgraph pattern and optionally a replacement graph.
classmethod
¶
build_from_verilog(
match_pattern_file: str,
replacement_pattern_file: str = "",
remove_ports: bool = True,
ignore_port_names: bool = False,
constraints: List[Constraint] = [],
) -> Pattern
Builds a Pattern instance from Verilog files.
Parameters:
-
(match_pattern_file¶str) –The path to the Verilog file containing the pattern to find.
-
(replacement_pattern_file¶str, default:'') –The path to the Verilog file containing the replacement pattern. If not specified, the pattern can only be used for analysis and not for modification. Defaults to ''.
-
(remove_ports¶bool, default:True) –Whether to remove all input and output ports of the patterns. Defaults to True. If set to True, all ports are removed, and only the instances inside the module (and the connections between them) are used as pattern. If set to False, the graph of the given modules is used directly, including its module ports. The matching algorithm will then only find matches, if the whole structure (including the module ports) is found!
-
(ignore_port_names¶bool, default:False) –Whether to check port names when trying to match the pattern against found instances. Defaults to False, in which case all port names must match the given pattern.
-
(constraints¶List[Constraint], default:[]) –List of constraints that need to be satisfied by any matching subgraphs. Defaults to [], which means no constraints are applied.
Returns:
-
Pattern(Pattern) –A Pattern instance representing the specified subgraph pattern and optionally a replacement graph.
classmethod
¶
build_from_yosys_netlists(
match_pattern_file: str,
replacement_pattern_file: str = "",
remove_ports: bool = True,
ignore_port_names: bool = False,
constraints: List[Constraint] = [],
) -> Pattern
Builds a Pattern instance from Yosys netlist files.
Parameters:
-
(match_pattern_file¶str) –The path to the Yosys netlist file containing the pattern to find.
-
(replacement_pattern_file¶str, default:'') –The path to the Yosys netlist file containing the replacement pattern. If not specified, the pattern can only be used for analysis and not for modification. Defaults to ''.
-
(remove_ports¶bool, default:True) –Whether to remove all input and output ports of the patterns. Defaults to True. If set to True, all ports are removed, and only the instances inside the module (and the connections between them) are used as pattern. If set to False, the graph of the given modules is used directly, including its module ports. The matching algorithm will then only find matches, if the whole structure (including the module ports) is found!
-
(ignore_port_names¶bool, default:False) –Whether to check port names when trying to match the pattern against found instances. Defaults to False, in which case all port names must match the given pattern.
-
(constraints¶List[Constraint], default:[]) –List of constraints that need to be satisfied by any matching subgraphs. Defaults to [], which means no constraints are applied.
Returns:
-
Pattern(Pattern) –A Pattern instance representing the specified subgraph pattern and optionally a replacement graph.